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Fingerprint Dive into the research topics where Chulwoo Kim is active. These topic labels come from the works of this person. Together they form a unique fingerprint.

  • 10 Similar Profiles
Clocks Engineering & Materials Science
Jitter Engineering & Materials Science
Electric power utilization Engineering & Materials Science
Electric potential Engineering & Materials Science
Networks (circuits) Engineering & Materials Science
Energy harvesting Engineering & Materials Science
Phase locked loops Engineering & Materials Science
Dynamic random access storage Engineering & Materials Science

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Research Output 1996 2019

23.3 A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface

Park, H., Song, J., Lee, Y., Sim, J., Choi, J. & Kim, C., 2019 Mar 6, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., p. 382-384 3 p. 8662462. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; vol. 2019-February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Decision feedback equalizers
Pulse amplitude modulation
Transceivers
Interfaces (computer)
Data storage equipment

12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface

Lee, Y., Choi, Y. J. & Kim, C., 2018 Feb 20, ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 287-288 2 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Clocks
Bandwidth
Radiation
Electric potential

12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces

Lee, Y., Choi, Y., Song, J., Hwang, S., Bae, S. G., Jun, J. & Kim, C., 2018 Jan 1, (Accepted/In press) In : IEEE Journal of Solid-State Circuits.

Research output: Contribution to journalArticle

Clocks
Electric potential
Signal interference
Jitter
Transceivers

31% Reduction of power consumption using active inductor at TX and AC termination at RX for a low-power post-LPDDR4 interfaces

Yoo, J., Lee, Y., Choi, Y., Park, H., Lee, C. & Kim, C., 2018 Apr 2, International Conference on Electronics, Information and Communication, ICEIC 2018. Institute of Electrical and Electronics Engineers Inc., Vol. 2018-January. p. 1-4 4 p.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Jitter
Electric power utilization
Microstrip lines
Transceivers

A Δ∑-Modulator based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for PLL Loop Bandwidth

Bae, S. G., Hwang, S., Song, J., Lee, Y. & Kim, C., 2018 Jun 11, (Accepted/In press) In : IEEE Transactions on Circuits and Systems II: Express Briefs.

Research output: Contribution to journalArticle

Signal interference
Phase locked loops
Modulators
Clocks
Calibration