TY - JOUR
T1 - 10-bit 100-MS/s pipelined ADC using input-swapped opamp sharing and self-calibrated V/I converter
AU - Kim, Moo Young
AU - Kim, Jinwoo
AU - Lee, Tagjong
AU - Kim, Chulwoo
N1 - Funding Information:
Manuscript received November 03, 2009; revised March 08, 2010; accepted May 04, 2010. Date of publication June 28, 2010; date of current version July 27, 2011. This work was supported by the Korea Science and Engineering Foundation (KOSEF) Grant funded by the Korea Government (MEST) (R0A-2007-000-20059-0) and fabricated through the MPW of IC Design Education Center (IDEC) supported by the Korea Ministry of Knowledge Economy (MKE).
PY - 2011/8
Y1 - 2011/8
N2 - A 31 mW, 10-bit 100-MS/s pipelined analog-to-digital converter (ADC), which alleviates the memory effect occurring in the opamp-sharing technique, and automatically corrects the current error of the V/I converter, has been developed. The proposed ADC achieves low-power consumption, high noise immunity, and has a small area, by employing an input-swapped opamp-sharing technique that switches the summing node in an multiplying digital-to-analog converter and a V/I converter with a process, supply voltage, and temperature condition detector. The ADC shows a differential nonlinearity of less than 0.48 LSB, and an integral nonlinearity of less than 0.95 LSB. Also, an signal-to-noise-and- distortion ratio of 56.2 dB is measured with a 1 MHz input frequency. This has been implemented in a 0.18-μm CMOS process, and occupies 1.6 ×0.8 mm2 of active area.
AB - A 31 mW, 10-bit 100-MS/s pipelined analog-to-digital converter (ADC), which alleviates the memory effect occurring in the opamp-sharing technique, and automatically corrects the current error of the V/I converter, has been developed. The proposed ADC achieves low-power consumption, high noise immunity, and has a small area, by employing an input-swapped opamp-sharing technique that switches the summing node in an multiplying digital-to-analog converter and a V/I converter with a process, supply voltage, and temperature condition detector. The ADC shows a differential nonlinearity of less than 0.48 LSB, and an integral nonlinearity of less than 0.95 LSB. Also, an signal-to-noise-and- distortion ratio of 56.2 dB is measured with a 1 MHz input frequency. This has been implemented in a 0.18-μm CMOS process, and occupies 1.6 ×0.8 mm2 of active area.
KW - Opamp-sharing
KW - V/I converter
KW - pipelined analog-to-digital converter (ADC)
KW - self-calibration
KW - switched bias
UR - http://www.scopus.com/inward/record.url?scp=79960976755&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2010.2050915
DO - 10.1109/TVLSI.2010.2050915
M3 - Article
AN - SCOPUS:79960976755
SN - 1063-8210
VL - 19
SP - 1438
EP - 1447
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 8
M1 - 5492304
ER -