10-bit 100MS/s CMOS Pipelined A/D converter with 0.59pJ/conversion-step

Moo Young Kim, Jinwoo Kim, Tagjong Lee, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

A 31mW, 10-bit lOOMS/s pipelined ADC has been developed. The proposed ADC achieves low power consumption, high noise immunity, and small area by employing a new opamp sharing technique that switches the summing node in an MDAC and a current source with a PVT condition detector. The ADC shows a DNL of less than 0.48 LSB and an INL of less than 0.95 LSB. Also, a SNDR of 56.2dB is measured with a 1MHz input frequency. It has been implemented in a 0.18um CMOS process and it occupies 1.6 × 0.8 mm2 of active area.

Original languageEnglish
Title of host publicationProceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Pages65-68
Number of pages4
DOIs
Publication statusPublished - 2008 Dec 1
Event2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, Japan
Duration: 2008 Nov 32008 Nov 5

Other

Other2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
CountryJapan
CityFukuoka
Period08/11/308/11/5

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of '10-bit 100MS/s CMOS Pipelined A/D converter with 0.59pJ/conversion-step'. Together they form a unique fingerprint.

  • Cite this

    Kim, M. Y., Kim, J., Lee, T., & Kim, C. (2008). 10-bit 100MS/s CMOS Pipelined A/D converter with 0.59pJ/conversion-step. In Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 (pp. 65-68). [4708730] https://doi.org/10.1109/ASSCC.2008.4708730