Abstract
This paper presents a new pin/energy-efficient data and clock signaling scheme, named braid clock signaling (BCS). This signaling scheme efficiently embeds clock information into the data stream without data overhead, unnecessary pins, and channels for clock. To remove the data overhead, the clock information is embedded in every other data period. This high transition density (TD) leads to the enhanced jitter tracking performance of a receiver and increased stability. Furthermore, a spread transition scheme (STS) removes the additional power consumption for the embedded clock with little electromagnetic interference (EMI). As non-return-to-zero (NRZ) signaling uses only two voltage levels, the NRZ BCS secures a large input voltage margin at the receiver side, unlike other pin-efficient multi-level signaling schemes. An analysis of the secured voltage margin shows improved energy efficiency over conventional pin-efficient multi-level signaling schemes, even without consideration of their clocking power dissipation. The prototype transceiver is fabricated in a 28-nm CMOS process with a 12-Gb/s delay-locked loop (DLL)-based receiver over four lines.
| Original language | English |
|---|---|
| Journal | IEEE Journal of Solid-State Circuits |
| DOIs | |
| Publication status | Accepted/In press - 2018 Jan 1 |
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Keywords
- Braid clock signaling (BCS)
- clock extraction
- clock-embedded signaling (CES)
- electromagnetic interference (EMI)
- intra-panel interface (IPI)
- low power
- receiver margin
- transceiver
- transition density (TD).
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces. / Lee, Yeonho; Choi, Yoonjae; Song, Junyoung; Hwang, Sewook; Bae, Sang Geun; Jun, Jaehun; Kim, Chulwoo.
In: IEEE Journal of Solid-State Circuits, 01.01.2018.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - 12-Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling With No Data Overhead and Spread Transition Scheme for 8K UHD Intra-Panel Interfaces
AU - Lee, Yeonho
AU - Choi, Yoonjae
AU - Song, Junyoung
AU - Hwang, Sewook
AU - Bae, Sang Geun
AU - Jun, Jaehun
AU - Kim, Chulwoo
PY - 2018/1/1
Y1 - 2018/1/1
N2 - This paper presents a new pin/energy-efficient data and clock signaling scheme, named braid clock signaling (BCS). This signaling scheme efficiently embeds clock information into the data stream without data overhead, unnecessary pins, and channels for clock. To remove the data overhead, the clock information is embedded in every other data period. This high transition density (TD) leads to the enhanced jitter tracking performance of a receiver and increased stability. Furthermore, a spread transition scheme (STS) removes the additional power consumption for the embedded clock with little electromagnetic interference (EMI). As non-return-to-zero (NRZ) signaling uses only two voltage levels, the NRZ BCS secures a large input voltage margin at the receiver side, unlike other pin-efficient multi-level signaling schemes. An analysis of the secured voltage margin shows improved energy efficiency over conventional pin-efficient multi-level signaling schemes, even without consideration of their clocking power dissipation. The prototype transceiver is fabricated in a 28-nm CMOS process with a 12-Gb/s delay-locked loop (DLL)-based receiver over four lines.
AB - This paper presents a new pin/energy-efficient data and clock signaling scheme, named braid clock signaling (BCS). This signaling scheme efficiently embeds clock information into the data stream without data overhead, unnecessary pins, and channels for clock. To remove the data overhead, the clock information is embedded in every other data period. This high transition density (TD) leads to the enhanced jitter tracking performance of a receiver and increased stability. Furthermore, a spread transition scheme (STS) removes the additional power consumption for the embedded clock with little electromagnetic interference (EMI). As non-return-to-zero (NRZ) signaling uses only two voltage levels, the NRZ BCS secures a large input voltage margin at the receiver side, unlike other pin-efficient multi-level signaling schemes. An analysis of the secured voltage margin shows improved energy efficiency over conventional pin-efficient multi-level signaling schemes, even without consideration of their clocking power dissipation. The prototype transceiver is fabricated in a 28-nm CMOS process with a 12-Gb/s delay-locked loop (DLL)-based receiver over four lines.
KW - Braid clock signaling (BCS)
KW - clock extraction
KW - clock-embedded signaling (CES)
KW - electromagnetic interference (EMI)
KW - intra-panel interface (IPI)
KW - low power
KW - receiver margin
KW - transceiver
KW - transition density (TD).
UR - http://www.scopus.com/inward/record.url?scp=85056567830&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85056567830&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2018.2878814
DO - 10.1109/JSSC.2018.2878814
M3 - Article
AN - SCOPUS:85056567830
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
ER -