12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces

Yeonho Lee, Yoonjae Choi, Sang Geun Bae, Jaehun Jun, Junyoung Song, Sewook Hwang, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A point-to-point interface with a clock embedded scheme (CES) in Fig. 29.5.1 is generally adopted in an intra-panel interface due to the poor signal integrity of the multi-drop topology, data and clock channel skews and EMI emission from the forwarded clock signal channels. Clock recovery in RX without a reference clock channel is usually carried out using one of two type of data encoding schemes, embedded clock with dummy clock bits [1-2,5] or ensured transition density with data encoding such as 8B10B encoding [3]. However, these two schemes reduce the effective bandwidth because they require over 20% overhead in the data stream. Although highly efficient signaling schemes have been introduced recently in the literature [4] to cope with the physical limitations of the process and channel, it is difficult to adopt these multi-level signaling schemes in intra-panel interfaces where there is a highly resistive channel of Chip-On-Glass and a ground bouncing problem [5] due to different voltage domains (1V and 8V-30V) for serial link and source drivers. This paper introduces a braid clock signaling (BCS) scheme which has the following advantages: 1) clock information without redundant bits; 2) NRZ signal levels for high voltage margin; and 3) low EMI emission with a random data dependent encoding and a spread transition scheme.

Original languageEnglish
Title of host publication2017 IEEE International Solid-State Circuits Conference, ISSCC 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages490-491
Number of pages2
Volume60
ISBN (Electronic)9781509037575
DOIs
Publication statusPublished - 2017 Mar 2
Event64th IEEE International Solid-State Circuits Conference, ISSCC 2017 - San Francisco, United States
Duration: 2017 Feb 52017 Feb 9

Other

Other64th IEEE International Solid-State Circuits Conference, ISSCC 2017
CountryUnited States
CitySan Francisco
Period17/2/517/2/9

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Lee, Y., Choi, Y., Bae, S. G., Jun, J., Song, J., Hwang, S., & Kim, C. (2017). 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfaces. In 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017 (Vol. 60, pp. 490-491). [7870475] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2017.7870475