12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface

Yeonho Lee, Yoon Jae Choi, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a Braid clock signaling scheme with 100% data payload and spread transition scheme. The Braid clock signaling has NRZ signaling margin without any dummy clock bits. Also, this paper describes spread transition schemes for low EMI radiation. The effective data bandwidth is increased by 11.1% with the 500% highly embedded transitions. With a same RX voltage margin, the required power for the termination is 5.4 times smaller than the multi-level signaling.

Original languageEnglish
Title of host publicationASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages287-288
Number of pages2
Volume2018-January
ISBN (Electronic)9781509006021
DOIs
Publication statusPublished - 2018 Feb 20
Event23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018 - Jeju, Korea, Republic of
Duration: 2018 Jan 222018 Jan 25

Other

Other23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018
CountryKorea, Republic of
CityJeju
Period18/1/2218/1/25

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Fingerprint Dive into the research topics of '12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interface'. Together they form a unique fingerprint.

Cite this