Abstract
Performance improvements in mobile devices with multi-cores and enhanced graphics quality requires higher memory bandwidth. Consequently, the design of I/O becomes a crucial issue [1]. In the LPDDR interface, a ground-terminated interface is used for a low-noise termination voltage (V<inf>ss</inf>) and small I/O capacitance (C<inf>IO</inf>) [2,3]. Even through noise margins and power efficiency are enhanced by ground termination, to compensate channel loss, the I/O is still the most power-hungry block. The pre-emphasized output driver and DFE are widely used to remove ISI and maximize read/write margins. However, multiple-taps in the output driver and the DFE are required to cover the channel loss, and they degrade the power efficiency of the I/O and occupy a large area.
| Original language | English |
|---|---|
| Title of host publication | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 320-321 |
| Number of pages | 2 |
| Volume | 58 |
| ISBN (Print) | 9781479962235 |
| DOIs | |
| Publication status | Published - 2015 Mar 17 |
| Event | 2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers - San Francisco, United States Duration: 2015 Feb 22 → 2015 Feb 26 |
Other
| Other | 2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers |
|---|---|
| Country | United States |
| City | San Francisco |
| Period | 15/2/22 → 15/2/26 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
Cite this
1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces. / Song, Junyoung; Lee, Hyun Woo; Kim, Jayoung; Hwang, Sewook; Kim, Chulwoo.
Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 58 Institute of Electrical and Electronics Engineers Inc., 2015. p. 320-321 7063055.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces
AU - Song, Junyoung
AU - Lee, Hyun Woo
AU - Kim, Jayoung
AU - Hwang, Sewook
AU - Kim, Chulwoo
PY - 2015/3/17
Y1 - 2015/3/17
N2 - Performance improvements in mobile devices with multi-cores and enhanced graphics quality requires higher memory bandwidth. Consequently, the design of I/O becomes a crucial issue [1]. In the LPDDR interface, a ground-terminated interface is used for a low-noise termination voltage (Vss) and small I/O capacitance (CIO) [2,3]. Even through noise margins and power efficiency are enhanced by ground termination, to compensate channel loss, the I/O is still the most power-hungry block. The pre-emphasized output driver and DFE are widely used to remove ISI and maximize read/write margins. However, multiple-taps in the output driver and the DFE are required to cover the channel loss, and they degrade the power efficiency of the I/O and occupy a large area.
AB - Performance improvements in mobile devices with multi-cores and enhanced graphics quality requires higher memory bandwidth. Consequently, the design of I/O becomes a crucial issue [1]. In the LPDDR interface, a ground-terminated interface is used for a low-noise termination voltage (Vss) and small I/O capacitance (CIO) [2,3]. Even through noise margins and power efficiency are enhanced by ground termination, to compensate channel loss, the I/O is still the most power-hungry block. The pre-emphasized output driver and DFE are widely used to remove ISI and maximize read/write margins. However, multiple-taps in the output driver and the DFE are required to cover the channel loss, and they degrade the power efficiency of the I/O and occupy a large area.
UR - http://www.scopus.com/inward/record.url?scp=84940772749&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84940772749&partnerID=8YFLogxK
U2 - 10.1109/ISSCC.2015.7063055
DO - 10.1109/ISSCC.2015.7063055
M3 - Conference contribution
AN - SCOPUS:84940772749
SN - 9781479962235
VL - 58
SP - 320
EP - 321
BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
PB - Institute of Electrical and Electronics Engineers Inc.
ER -