1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces

Junyoung Song, Hyun Woo Lee, Jayoung Kim, Sewook Hwang, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

Performance improvements in mobile devices with multi-cores and enhanced graphics quality requires higher memory bandwidth. Consequently, the design of I/O becomes a crucial issue [1]. In the LPDDR interface, a ground-terminated interface is used for a low-noise termination voltage (V<inf>ss</inf>) and small I/O capacitance (C<inf>IO</inf>) [2,3]. Even through noise margins and power efficiency are enhanced by ground termination, to compensate channel loss, the I/O is still the most power-hungry block. The pre-emphasized output driver and DFE are widely used to remove ISI and maximize read/write margins. However, multiple-taps in the output driver and the DFE are required to cover the channel loss, and they degrade the power efficiency of the I/O and occupy a large area.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages320-321
Number of pages2
Volume58
ISBN (Print)9781479962235
DOIs
Publication statusPublished - 2015 Mar 17
Event2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers - San Francisco, United States
Duration: 2015 Feb 222015 Feb 26

Other

Other2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers
CountryUnited States
CitySan Francisco
Period15/2/2215/2/26

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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    Song, J., Lee, H. W., Kim, J., Hwang, S., & Kim, C. (2015). 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 58, pp. 320-321). [7063055] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2015.7063055