1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces

Junyoung Song; Hyun Woo Lee; Jayoung Kim; Sewook Hwang; Chulwoo Kim

doi:10.1109/ISSCC.2015.7063055

1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces

Junyoung Song, Hyun Woo Lee, Jayoung Kim, Sewook Hwang, Chulwoo Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Citations (Scopus)

Abstract

Performance improvements in mobile devices with multi-cores and enhanced graphics quality requires higher memory bandwidth. Consequently, the design of I/O becomes a crucial issue [1]. In the LPDDR interface, a ground-terminated interface is used for a low-noise termination voltage (V_ss) and small I/O capacitance (C_IO) [2,3]. Even through noise margins and power efficiency are enhanced by ground termination, to compensate channel loss, the I/O is still the most power-hungry block. The pre-emphasized output driver and DFE are widely used to remove ISI and maximize read/write margins. However, multiple-taps in the output driver and the DFE are required to cover the channel loss, and they degrade the power efficiency of the I/O and occupy a large area.

Original language	English
Title of host publication	2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	320-321
Number of pages	2
ISBN (Electronic)	9781479962235
DOIs	https://doi.org/10.1109/ISSCC.2015.7063055
Publication status	Published - 2015 Mar 17
Event	2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers - San Francisco, United States Duration: 2015 Feb 22 → 2015 Feb 26

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	58
ISSN (Print)	0193-6530

Other

Other	2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers
Country/Territory	United States
City	San Francisco
Period	15/2/22 → 15/2/26

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISSCC.2015.7063055

Cite this

Song, J., Lee, H. W., Kim, J., Hwang, S., & Kim, C. (2015). 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces. In 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers (pp. 320-321). [7063055] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 58). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2015.7063055

1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces. / Song, Junyoung; Lee, Hyun Woo; Kim, Jayoung et al.

2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. p. 320-321 7063055 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 58).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Song, J, Lee, HW, Kim, J, Hwang, S & Kim, C 2015, 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces. in 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers., 7063055, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 58, Institute of Electrical and Electronics Engineers Inc., pp. 320-321, 2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers, San Francisco, United States, 15/2/22. https://doi.org/10.1109/ISSCC.2015.7063055

Song J, Lee HW, Kim J, Hwang S, Kim C. 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces. In 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2015. p. 320-321. 7063055. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2015.7063055

Song, Junyoung ; Lee, Hyun Woo ; Kim, Jayoung et al. / 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces. 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 320-321 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

@inproceedings{c2710a8e581e4d0eb89258e5782d08e6,

title = "1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces",

abstract = "Performance improvements in mobile devices with multi-cores and enhanced graphics quality requires higher memory bandwidth. Consequently, the design of I/O becomes a crucial issue [1]. In the LPDDR interface, a ground-terminated interface is used for a low-noise termination voltage (Vss) and small I/O capacitance (CIO) [2,3]. Even through noise margins and power efficiency are enhanced by ground termination, to compensate channel loss, the I/O is still the most power-hungry block. The pre-emphasized output driver and DFE are widely used to remove ISI and maximize read/write margins. However, multiple-taps in the output driver and the DFE are required to cover the channel loss, and they degrade the power efficiency of the I/O and occupy a large area.",

author = "Junyoung Song and Lee, {Hyun Woo} and Jayoung Kim and Sewook Hwang and Chulwoo Kim",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers ; Conference date: 22-02-2015 Through 26-02-2015",

year = "2015",

month = mar,

day = "17",

doi = "10.1109/ISSCC.2015.7063055",

language = "English",

series = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "320--321",

booktitle = "2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers",

}

TY - GEN

T1 - 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces

AU - Song, Junyoung

AU - Lee, Hyun Woo

AU - Kim, Jayoung

AU - Hwang, Sewook

AU - Kim, Chulwoo

PY - 2015/3/17

Y1 - 2015/3/17

N2 - Performance improvements in mobile devices with multi-cores and enhanced graphics quality requires higher memory bandwidth. Consequently, the design of I/O becomes a crucial issue [1]. In the LPDDR interface, a ground-terminated interface is used for a low-noise termination voltage (Vss) and small I/O capacitance (CIO) [2,3]. Even through noise margins and power efficiency are enhanced by ground termination, to compensate channel loss, the I/O is still the most power-hungry block. The pre-emphasized output driver and DFE are widely used to remove ISI and maximize read/write margins. However, multiple-taps in the output driver and the DFE are required to cover the channel loss, and they degrade the power efficiency of the I/O and occupy a large area.

AB - Performance improvements in mobile devices with multi-cores and enhanced graphics quality requires higher memory bandwidth. Consequently, the design of I/O becomes a crucial issue [1]. In the LPDDR interface, a ground-terminated interface is used for a low-noise termination voltage (Vss) and small I/O capacitance (CIO) [2,3]. Even through noise margins and power efficiency are enhanced by ground termination, to compensate channel loss, the I/O is still the most power-hungry block. The pre-emphasized output driver and DFE are widely used to remove ISI and maximize read/write margins. However, multiple-taps in the output driver and the DFE are required to cover the channel loss, and they degrade the power efficiency of the I/O and occupy a large area.

UR - http://www.scopus.com/inward/record.url?scp=84940772749&partnerID=8YFLogxK

U2 - 10.1109/ISSCC.2015.7063055

DO - 10.1109/ISSCC.2015.7063055

M3 - Conference contribution

AN - SCOPUS:84940772749

T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

SP - 320

EP - 321

BT - 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers

Y2 - 22 February 2015 through 26 February 2015

ER -

1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces

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