24-Gb/s Input-Data-Independent Clock and Data Recovery Utilizing Bit-Efficient Braid Clock Signaling With Fixed Embedded Transition for 8K-UHD Intrapanel Interface

Yeonho Lee, Yoonjae Choi, Jonghyuk Choi, Chulwoo Kim

Research output: Contribution to journalArticle

Abstract

Input-data-independent clock and data recovery (CDR) employing bit-efficient braid clock signaling (BCS) for raw data transmission is presented for a point-to-point post-8K ultrahigh-definition (UHD) intrapanel interface at 24 Gb/s. The effect of input data pattern on CDR is analyzed, and the proposed bit-efficient BCS scheme for phase-locked loop (PLL)-based CDR eliminates the jitter-peaking dependency on the input data pattern. The removal of this dependency with the proposed BCS scheme decreases the loop filter size without jitter peaking and the bit error rate (BER). The prototype CDR has been fabricated using a 28-nm CMOS process and occupies an area of 0.024 mm2. The 24-Gb/s PLL-based CDR design with the BCS scheme consumes 13.4 mW. The CDR with BCS scheme achieves a recovered clock long-term jitter of 5.11 ps rms/37.5 ps p-p and a reduction in jitter peaking of 27 dB with a small-sized loop filter and six repeated consecutive identical digits in the stream of a PRBS7 pattern.

Original languageEnglish
Article number8718803
Pages (from-to)21-24
Number of pages4
JournalIEEE Solid-State Circuits Letters
Volume2
Issue number3
DOIs
Publication statusPublished - 2019 Mar

Keywords

  • Braid clock signaling (BCS)
  • clock and data recovery (CDR)
  • clock embedded signaling (CES)
  • consecutive identical digits (CIDs)
  • input-data-independent CDR (IDI-CDR)
  • intrapanel interface (IPI)
  • jitter peaking
  • receiver

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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