2.5 V, 10-bit, 50-MS/s CMOS pipeline low power A/D converter

Dae Yong Kim, Gil Su Kim, Hoon Jae Ki, Soo Won Kim

Research output: Contribution to conferencePaper

Abstract

In this paper, we present A/D converter for signal processing of infrared sensor and CMOS image sensor. The A/D converter implemented in a 0.25um CMOS process provides a resolution of 10bits at a sampling rate of 50MS/s while dissipating 67mW from 2.5V supply voltage. This A/D converter is based on a pipelined architecture in which the number of bits converted per stage and the stage number are optimized to simultaneously achieve the desired linearity and reduce power consumption as well. Simulation results show that the A/D converter using 1.5bit per stage MDAC with switched capacitors and dynamic comparators efficiently reduces the power consumption.

Original languageEnglish
Publication statusPublished - 2003 Jan 1
Event8th International Workshop on ADC Modelling and Testing, IWADC 2003 - Perugia, Italy
Duration: 2003 Sep 82003 Sep 10

Conference

Conference8th International Workshop on ADC Modelling and Testing, IWADC 2003
CountryItaly
CityPerugia
Period03/9/803/9/10

Keywords

  • 1.5bit per stage
  • Analog-to-digital converter
  • MDAC
  • Pipeline ADC
  • Switched-capacitor circuits

ASJC Scopus subject areas

  • Modelling and Simulation

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  • Cite this

    Kim, D. Y., Kim, G. S., Ki, H. J., & Kim, S. W. (2003). 2.5 V, 10-bit, 50-MS/s CMOS pipeline low power A/D converter. Paper presented at 8th International Workshop on ADC Modelling and Testing, IWADC 2003, Perugia, Italy.