25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector

Hyun Woo Lee, Junyoung Song, Sang Ah Hyun, Seunggeun Baek, Yuri Lim, Jungwan Lee, Minsu Park, Haerang Choi, Changkyu Choi, Jinyoup Cha, Jaeil Kim, Hoon Choi, Seungwook Kwack, Yonggu Kang, Jongsam Kim, Junghoon Park, Jonghwan Kim, Jinhee Cho, Chulwoo Kim, Yunsaing KimJaejin Lee, Byongtae Chung, Sungjoo Hong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The demand for high-bandwidth memories is increasing with an increase in the need for high-performance systems. Wide-I/O memory and GDDR5 are two types of high-bandwidth memories. GDDR5 is more compatible than wide I/O for contemporary systems, such as graphics cards and game consoles. The datarate of GDDR5 has reached 7Gb/s/pin. However, the power consumption and cost have increased owing to high-performance-oriented designs, die penalties, and additional test costs. DDR4 is an alternative low-cost memory with high performance in the range of 2.4 to 3.2Gb/s/pin [1]. However it is difficult for DDR4 DRAM to raise the 3.2Gb/s/pin bin portion to lower the cost. In DRAMs, the standby power and self-refresh power are more important than the operating power because DRAMs are mainly in the standby or self-refresh mode in systems. As the operating speed increases, the data window is narrowed, and the jitter increases. Therefore, a duty-cycle corrector (DCC) is employed to increase the data window when the external clock duty cycle is distorted in GDDR5 [2]. The bang-bang jitter caused by the DCC is inevitable even if the external clock duty ratio is exactly 50%. Sometimes the DCC may distort the data window because of an internal DCC offset. This paper presents a GDDR5M (mainstream) memory for graphics cards and a small-outline dual-inline memory module) (SO-DIMM). The standby power is managed by the auto-sync mode. Additionally, the architecture of GDDR5M is similar to that of DDR4, and not GDDR5. The error-adaptive DCC can remove the initial duty-cycle offset automatically and remove the bang-bang jitter when the duty cycle of the external clock is not distorted.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages434-435
Number of pages2
Volume57
DOIs
Publication statusPublished - 2014 Apr 14
Event2014 61st IEEE International Solid-State Circuits Conference, ISSCC 2014 - San Francisco, CA, United States
Duration: 2014 Feb 92014 Feb 13

Other

Other2014 61st IEEE International Solid-State Circuits Conference, ISSCC 2014
CountryUnited States
CitySan Francisco, CA
Period14/2/914/2/13

Fingerprint

Data storage equipment
Dynamic random access storage
Jitter
Clocks
Costs
Bandwidth
Bins
Electric power utilization

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Lee, H. W., Song, J., Hyun, S. A., Baek, S., Lim, Y., Lee, J., ... Hong, S. (2014). 25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (Vol. 57, pp. 434-435). [6757502] https://doi.org/10.1109/ISSCC.2014.6757502

25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. / Lee, Hyun Woo; Song, Junyoung; Hyun, Sang Ah; Baek, Seunggeun; Lim, Yuri; Lee, Jungwan; Park, Minsu; Choi, Haerang; Choi, Changkyu; Cha, Jinyoup; Kim, Jaeil; Choi, Hoon; Kwack, Seungwook; Kang, Yonggu; Kim, Jongsam; Park, Junghoon; Kim, Jonghwan; Cho, Jinhee; Kim, Chulwoo; Kim, Yunsaing; Lee, Jaejin; Chung, Byongtae; Hong, Sungjoo.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 57 2014. p. 434-435 6757502.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lee, HW, Song, J, Hyun, SA, Baek, S, Lim, Y, Lee, J, Park, M, Choi, H, Choi, C, Cha, J, Kim, J, Choi, H, Kwack, S, Kang, Y, Kim, J, Park, J, Kim, J, Cho, J, Kim, C, Kim, Y, Lee, J, Chung, B & Hong, S 2014, 25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference. vol. 57, 6757502, pp. 434-435, 2014 61st IEEE International Solid-State Circuits Conference, ISSCC 2014, San Francisco, CA, United States, 14/2/9. https://doi.org/10.1109/ISSCC.2014.6757502
Lee HW, Song J, Hyun SA, Baek S, Lim Y, Lee J et al. 25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 57. 2014. p. 434-435. 6757502 https://doi.org/10.1109/ISSCC.2014.6757502
Lee, Hyun Woo ; Song, Junyoung ; Hyun, Sang Ah ; Baek, Seunggeun ; Lim, Yuri ; Lee, Jungwan ; Park, Minsu ; Choi, Haerang ; Choi, Changkyu ; Cha, Jinyoup ; Kim, Jaeil ; Choi, Hoon ; Kwack, Seungwook ; Kang, Yonggu ; Kim, Jongsam ; Park, Junghoon ; Kim, Jonghwan ; Cho, Jinhee ; Kim, Chulwoo ; Kim, Yunsaing ; Lee, Jaejin ; Chung, Byongtae ; Hong, Sungjoo. / 25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 57 2014. pp. 434-435
@inproceedings{49185f1724e944999659b43f657fe6c4,
title = "25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector",
abstract = "The demand for high-bandwidth memories is increasing with an increase in the need for high-performance systems. Wide-I/O memory and GDDR5 are two types of high-bandwidth memories. GDDR5 is more compatible than wide I/O for contemporary systems, such as graphics cards and game consoles. The datarate of GDDR5 has reached 7Gb/s/pin. However, the power consumption and cost have increased owing to high-performance-oriented designs, die penalties, and additional test costs. DDR4 is an alternative low-cost memory with high performance in the range of 2.4 to 3.2Gb/s/pin [1]. However it is difficult for DDR4 DRAM to raise the 3.2Gb/s/pin bin portion to lower the cost. In DRAMs, the standby power and self-refresh power are more important than the operating power because DRAMs are mainly in the standby or self-refresh mode in systems. As the operating speed increases, the data window is narrowed, and the jitter increases. Therefore, a duty-cycle corrector (DCC) is employed to increase the data window when the external clock duty cycle is distorted in GDDR5 [2]. The bang-bang jitter caused by the DCC is inevitable even if the external clock duty ratio is exactly 50{\%}. Sometimes the DCC may distort the data window because of an internal DCC offset. This paper presents a GDDR5M (mainstream) memory for graphics cards and a small-outline dual-inline memory module) (SO-DIMM). The standby power is managed by the auto-sync mode. Additionally, the architecture of GDDR5M is similar to that of DDR4, and not GDDR5. The error-adaptive DCC can remove the initial duty-cycle offset automatically and remove the bang-bang jitter when the duty cycle of the external clock is not distorted.",
author = "Lee, {Hyun Woo} and Junyoung Song and Hyun, {Sang Ah} and Seunggeun Baek and Yuri Lim and Jungwan Lee and Minsu Park and Haerang Choi and Changkyu Choi and Jinyoup Cha and Jaeil Kim and Hoon Choi and Seungwook Kwack and Yonggu Kang and Jongsam Kim and Junghoon Park and Jonghwan Kim and Jinhee Cho and Chulwoo Kim and Yunsaing Kim and Jaejin Lee and Byongtae Chung and Sungjoo Hong",
year = "2014",
month = "4",
day = "14",
doi = "10.1109/ISSCC.2014.6757502",
language = "English",
isbn = "9781479909186",
volume = "57",
pages = "434--435",
booktitle = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

}

TY - GEN

T1 - 25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector

AU - Lee, Hyun Woo

AU - Song, Junyoung

AU - Hyun, Sang Ah

AU - Baek, Seunggeun

AU - Lim, Yuri

AU - Lee, Jungwan

AU - Park, Minsu

AU - Choi, Haerang

AU - Choi, Changkyu

AU - Cha, Jinyoup

AU - Kim, Jaeil

AU - Choi, Hoon

AU - Kwack, Seungwook

AU - Kang, Yonggu

AU - Kim, Jongsam

AU - Park, Junghoon

AU - Kim, Jonghwan

AU - Cho, Jinhee

AU - Kim, Chulwoo

AU - Kim, Yunsaing

AU - Lee, Jaejin

AU - Chung, Byongtae

AU - Hong, Sungjoo

PY - 2014/4/14

Y1 - 2014/4/14

N2 - The demand for high-bandwidth memories is increasing with an increase in the need for high-performance systems. Wide-I/O memory and GDDR5 are two types of high-bandwidth memories. GDDR5 is more compatible than wide I/O for contemporary systems, such as graphics cards and game consoles. The datarate of GDDR5 has reached 7Gb/s/pin. However, the power consumption and cost have increased owing to high-performance-oriented designs, die penalties, and additional test costs. DDR4 is an alternative low-cost memory with high performance in the range of 2.4 to 3.2Gb/s/pin [1]. However it is difficult for DDR4 DRAM to raise the 3.2Gb/s/pin bin portion to lower the cost. In DRAMs, the standby power and self-refresh power are more important than the operating power because DRAMs are mainly in the standby or self-refresh mode in systems. As the operating speed increases, the data window is narrowed, and the jitter increases. Therefore, a duty-cycle corrector (DCC) is employed to increase the data window when the external clock duty cycle is distorted in GDDR5 [2]. The bang-bang jitter caused by the DCC is inevitable even if the external clock duty ratio is exactly 50%. Sometimes the DCC may distort the data window because of an internal DCC offset. This paper presents a GDDR5M (mainstream) memory for graphics cards and a small-outline dual-inline memory module) (SO-DIMM). The standby power is managed by the auto-sync mode. Additionally, the architecture of GDDR5M is similar to that of DDR4, and not GDDR5. The error-adaptive DCC can remove the initial duty-cycle offset automatically and remove the bang-bang jitter when the duty cycle of the external clock is not distorted.

AB - The demand for high-bandwidth memories is increasing with an increase in the need for high-performance systems. Wide-I/O memory and GDDR5 are two types of high-bandwidth memories. GDDR5 is more compatible than wide I/O for contemporary systems, such as graphics cards and game consoles. The datarate of GDDR5 has reached 7Gb/s/pin. However, the power consumption and cost have increased owing to high-performance-oriented designs, die penalties, and additional test costs. DDR4 is an alternative low-cost memory with high performance in the range of 2.4 to 3.2Gb/s/pin [1]. However it is difficult for DDR4 DRAM to raise the 3.2Gb/s/pin bin portion to lower the cost. In DRAMs, the standby power and self-refresh power are more important than the operating power because DRAMs are mainly in the standby or self-refresh mode in systems. As the operating speed increases, the data window is narrowed, and the jitter increases. Therefore, a duty-cycle corrector (DCC) is employed to increase the data window when the external clock duty cycle is distorted in GDDR5 [2]. The bang-bang jitter caused by the DCC is inevitable even if the external clock duty ratio is exactly 50%. Sometimes the DCC may distort the data window because of an internal DCC offset. This paper presents a GDDR5M (mainstream) memory for graphics cards and a small-outline dual-inline memory module) (SO-DIMM). The standby power is managed by the auto-sync mode. Additionally, the architecture of GDDR5M is similar to that of DDR4, and not GDDR5. The error-adaptive DCC can remove the initial duty-cycle offset automatically and remove the bang-bang jitter when the duty cycle of the external clock is not distorted.

UR - http://www.scopus.com/inward/record.url?scp=84898079938&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84898079938&partnerID=8YFLogxK

U2 - 10.1109/ISSCC.2014.6757502

DO - 10.1109/ISSCC.2014.6757502

M3 - Conference contribution

AN - SCOPUS:84898079938

SN - 9781479909186

VL - 57

SP - 434

EP - 435

BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

ER -