2.5GHz PLL with current matching charge-pump for 10Gbps transmitter design

Jaehong Ko, Wookwan Lee, Soo Won Kim

Research output: Contribution to conferencePaper

2 Citations (Scopus)

Abstract

In this paper, we describe a mixed PLL architecture for low jitter clock generation that use a proposed charge pump and output buffer. The newly designed charge-pump circuit is composed of two differential inputs, the signals of UP and DN from the PFD, and an op-amp that matches between the upper current and the lower current. If the two currents are matched in charge-pump there is a low ripple voltage, which is VCO control voltage. The new charge pump circuit has a good immunity from MOSFET width and length variation. Also, we build the differential current driving output buffer for high speed signal processing on a chip. In the newly designed output buffer circuits, the push-pull source follower is added to the previous differential current driving output buffer. As the result, the jitter characteristic has been improved. The PLL with current matching charge-pump has been designed by 0.18μm one-poly four metal CMOS technology and simulated by HSPICE. From the simulation results, it is shown that the VCO control voltage is at least 0.6mV.

Original languageEnglish
Pages122-125
Number of pages4
Publication statusPublished - 2005 Dec 29
Event2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05 - Chicago, IL, United States
Duration: 2005 Apr 172005 Apr 19

Other

Other2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05
CountryUnited States
CityChicago, IL
Period05/4/1705/4/19

Keywords

  • Charge-pump
  • Jitter
  • Output Buffer
  • PLL

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Ko, J., Lee, W., & Kim, S. W. (2005). 2.5GHz PLL with current matching charge-pump for 10Gbps transmitter design. 122-125. Paper presented at 2005 ACM Great Lakessymposium on VLSI, GLSVLSI'05, Chicago, IL, United States.