True random number generators (TRNGs) are important in data encryption for information security applications. In this paper, we propose a TRNG that utilizes a comparator in the common-mode operation and the sampling uncertainty of a D flip-flop (DFF). The comparator output is affected by the input common-mode noise and the noise that is simultaneously self-induced. A slicer generates an unpredictable and asynchronous pulse to the input of the DFF according to the output-referred noise of the comparator. By sampling the random pulse with a 3-GHz external clock, there is a sampling uncertainty, which helps to increase the random quality. As a result, we use the independent two random sources for TRNG. The area of the designed circuit is 1609 μm2. In spite of the small size, the data rate of the proposed TRNG is 3 Gb/s. We verify that the output bit stream passes all of the National Institute of Standards and Technology test suites. We fabricate the TRNG in a 65-nm CMOS process with a 1.2 V supply voltage. The power consumption of the proposed TRNG is 5 mW, and the energy per bit is 1.6 pJ/b.
- Data encryption
- National Institute of Standards and Technology (NIST) test
- true random number generator (TRNG)
ASJC Scopus subject areas
- Electrical and Electronic Engineering