A 30-Gb/s three-level pulse amplitude modulation (PAM-3) transceiver is designed with a one-tap tri-level decision feedback equalizer (DFE) to realize a high-speed dynamic random access memory (DRAM) interface via the 28-nm CMOS process. A 1.5-bit/pin bit efficiency is achieved by encoding and decoding 3-bit data in two unit intervals (UIs). The half-rate PAM-3 transmitter modulates single-ended pseudorandom binary sequence (PRBS) 7/15 data using a low-power encoding logic and an output driver. The receiver achieves a bit error rate (BER) of less than 1E-12 over an 80-mm FR-4 printed circuit board (PCB) channel. At the maximum data rate, the bit efficiency of the transceiver is 1.11 pJ/bit, consuming 33.4 mW. In the receiver, the attenuated PAM-3 data are equalized by a continuous-time linear equalizer (CTLE) and a one-tap tri-level DFE, which has the same complexity as that of non-return-to-zero (NRZ) signaling. The tri-state buffers, which have a floating PMOS switch, convert the output of the comparator into NRZ data, resulting in reduced delay and power dissipation. Four channels of the transceivers operate at data rates of up to 30 × 4 Gb/s, and the horizontal eye margin of the measured PAM-3 data is achieved at a UI of 0.14 for the PRBS-7 pattern at the maximum data rate.
- Decision feedback equalizer (DFE)
- double data rate (DDR)
- high-speed memory interface
- pulse amplitude modulation (PAM-3)
- single-ended interface
ASJC Scopus subject areas
- Electrical and Electronic Engineering