3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay

Basanth Jagannathan, Mounir Meghelli, Kevin Chan, Jae Sung Rieh, Kathryn Schonenberg, David Ahlgren, Seshadri Subbanna, Greg Freeman

Research output: Contribution to journalArticle

36 Citations (Scopus)

Abstract

We show empirical results that demonstrate the effect of high performance SiGe HBT design parameters on the minimum gate delay of an ECL ring oscillator. SiGe HBT devices with a high fMAX (338 GHz) and a low fT (180 GHz) achieve a minimum delay of 3.9 ps, which to our knowledge is the lowest reported delay for a silicon based logic gate. Compared to the extracted (extrapolated) fT and fMAX, a simple figure of merit proportional to √fT/RBCCB with RB and CCB extracted from S-parameter measurement is best correlated to the minimum gate delay.

Original languageEnglish
Pages (from-to)324-326
Number of pages3
JournalIEEE Electron Device Letters
Volume24
Issue number5
DOIs
Publication statusPublished - 2003 May 1

Keywords

  • Germanium
  • HBTs
  • High-speed devices
  • Ring oscillators
  • SiGe
  • Silicon

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Jagannathan, B., Meghelli, M., Chan, K., Rieh, J. S., Schonenberg, K., Ahlgren, D., Subbanna, S., & Freeman, G. (2003). 3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay. IEEE Electron Device Letters, 24(5), 324-326. https://doi.org/10.1109/LED.2003.812568