A Δ ∑ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth

Sang Geun Bae, Sewook Hwang, Junyoung Song, Yeonho Lee, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

A spread-spectrum clock generator (SSCG) is an essential building block for reducing electromagnetic interference (EMI) in a system-on-a-chip without shielding the device that increases the system cost and weight. In a Δ∑ modulator (DSM)-based SSCG, EMI reduction is degraded by attenuating the harmonic components of the generated profile owing to the phase-locked loop bandwidth (fLBW). This brief proposes a DSM-based SSCG with a digital compensator to maximize EMI reduction with a triangular profile. By adaptively reconfiguring the gains of the digital compensator, the proposed SSCG maintains the EMI reduction regardless of fLBW variations. The EMI reduction is improved by 2.17 dB at 1.35 GHz with the lowest fLBW. A prototype of the proposed SSCG is fabricated using 65-nm CMOS technology. The measured RMS jitter and power consumption are is 2.47 ps and 7 mW, respectively and the die occupies 0.292 mm2.

Original languageEnglish
Article number8382229
Pages (from-to)192-196
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume66
Issue number2
DOIs
Publication statusPublished - 2019 Feb

Keywords

  • EMI reduction
  • PLL
  • SSCG
  • digital compensation
  • spread-spectrum clock

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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