A 0.004-mm2 portable multiphase clock generator tile for 1.2-GHz RISC microprocessor

Inhwa Jung, Gunok Jung, Janghoon Song, Moo Young Kim, Junyoung Park, Sung Bae Park, Chulwoo Kim

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

Portable multiphase clock generators capable of adjusting its clock phase according to input clock frequencies have been developed both in a 0.18-μm and in a 0.13-μm CMOS technologies. They consist of a full-digital CMOS circuit design that leads to a simple, robust, and portable IP. In addition, their open-loop architecture lead to no jitter accumulation and one-cycle lock characteristic that enables clock-on-demand circuit structures. The implemented low power clock generator tile in a 0.13-μm CMOS technology occupies only 0.004 mm2 and operates at variable input frequencies ranging from 625 MHz to 1.2 GHz within a ± 2% phase error having one-cycle lock time.

Original languageEnglish
Pages (from-to)116-120
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume55
Issue number2
DOIs
Publication statusPublished - 2008

Keywords

  • Digital clock generator
  • Fast lock time
  • Low jitter
  • Low power

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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