A 0.004-mm2 portable multiphase clock generator tile for 1.2-GHz RISC microprocessor

Inhwa Jung; Gunok Jung; Janghoon Song; Moo Young Kim; Junyoung Park; Sung Bae Park; Chulwoo Kim

doi:10.1109/TCSII.2007.910798

A 0.004-mm² portable multiphase clock generator tile for 1.2-GHz RISC microprocessor

Inhwa Jung, Gunok Jung, Janghoon Song, Moo Young Kim, Junyoung Park, Sung Bae Park, Chulwoo Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

9 Citations (Scopus)

Abstract

Portable multiphase clock generators capable of adjusting its clock phase according to input clock frequencies have been developed both in a 0.18-μm and in a 0.13-μm CMOS technologies. They consist of a full-digital CMOS circuit design that leads to a simple, robust, and portable IP. In addition, their open-loop architecture lead to no jitter accumulation and one-cycle lock characteristic that enables clock-on-demand circuit structures. The implemented low power clock generator tile in a 0.13-μm CMOS technology occupies only 0.004 mm² and operates at variable input frequencies ranging from 625 MHz to 1.2 GHz within a ± 2% phase error having one-cycle lock time.

Original language	English
Pages (from-to)	116-120
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	55
Issue number	2
DOIs	https://doi.org/10.1109/TCSII.2007.910798
Publication status	Published - 2008

Keywords

Digital clock generator
Fast lock time
Low jitter
Low power

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/TCSII.2007.910798

Cite this

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title = "A 0.004-mm2 portable multiphase clock generator tile for 1.2-GHz RISC microprocessor",

abstract = "Portable multiphase clock generators capable of adjusting its clock phase according to input clock frequencies have been developed both in a 0.18-μm and in a 0.13-μm CMOS technologies. They consist of a full-digital CMOS circuit design that leads to a simple, robust, and portable IP. In addition, their open-loop architecture lead to no jitter accumulation and one-cycle lock characteristic that enables clock-on-demand circuit structures. The implemented low power clock generator tile in a 0.13-μm CMOS technology occupies only 0.004 mm2 and operates at variable input frequencies ranging from 625 MHz to 1.2 GHz within a ± 2% phase error having one-cycle lock time.",

keywords = "Digital clock generator, Fast lock time, Low jitter, Low power",

author = "Inhwa Jung and Gunok Jung and Janghoon Song and Kim, {Moo Young} and Junyoung Park and Park, {Sung Bae} and Chulwoo Kim",

note = "Funding Information: Manuscript received April 18, 2007; revised July 24, 2007. This work was supported by the SOC R&D Center of SAMSUNG Electronics Co. and financially supported by the Ministry of Education and Human Resources Development (MOE), the Ministry of Commerce, Industry and Energy (MOCIE), and the Ministry of Labor (MOLAB) through the fostering project of the Lab of Excellency. This paper was recommended by Associate Editor V. Kursun.",

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AU - Song, Janghoon

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AU - Park, Junyoung

AU - Park, Sung Bae

AU - Kim, Chulwoo

N1 - Funding Information: Manuscript received April 18, 2007; revised July 24, 2007. This work was supported by the SOC R&D Center of SAMSUNG Electronics Co. and financially supported by the Ministry of Education and Human Resources Development (MOE), the Ministry of Commerce, Industry and Energy (MOCIE), and the Ministry of Labor (MOLAB) through the fostering project of the Lab of Excellency. This paper was recommended by Associate Editor V. Kursun.

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AB - Portable multiphase clock generators capable of adjusting its clock phase according to input clock frequencies have been developed both in a 0.18-μm and in a 0.13-μm CMOS technologies. They consist of a full-digital CMOS circuit design that leads to a simple, robust, and portable IP. In addition, their open-loop architecture lead to no jitter accumulation and one-cycle lock characteristic that enables clock-on-demand circuit structures. The implemented low power clock generator tile in a 0.13-μm CMOS technology occupies only 0.004 mm2 and operates at variable input frequencies ranging from 625 MHz to 1.2 GHz within a ± 2% phase error having one-cycle lock time.

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