A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme

Dongsuk Shin, Won Joo Yun, Hyun Woo Lee, Young Jung Choi, Suki Kim, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

A wide-range low-jitter digital DLL using 0.18um single-poly four-metal CMOS technology is proposed that uses an open-loop time-to-digital converter (TDC)-based DCC circuit with 10 cycles of maximum locking time by virtue of pulse width detection scheme. In addition, the DLL uses a semi dual delay line to remove the boundary switching problem and to Optimize its area and power consumption. Thus, the proposed DLL operates over a frequency range from 170MHz to 1.4GHz. The peak-to-peak jitter is 13.8ps at 1.4GHz and the power consumption is reduced to 27mW.

Original languageEnglish
Title of host publicationESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference
Pages82-85
Number of pages4
DOIs
Publication statusPublished - 2008
Event34th European Solid-State Circuits Conference, ESSCIRC 2008 - Edinburgh, Scotland, United Kingdom
Duration: 2008 Sep 152008 Sep 19

Publication series

NameESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference

Other

Other34th European Solid-State Circuits Conference, ESSCIRC 2008
CountryUnited Kingdom
CityEdinburgh, Scotland
Period08/9/1508/9/19

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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