A 0.31-1 GHz fast-corrected duty-cycle corrector with successive approximation register for DDR DRAM applications

Young Jae Min, Chan Hui Jeong, Kyu Young Kim, Won Ho Choi, Jong Pil Son, Chulwoo Kim, Soo Won Kim

Research output: Contribution to journalArticle

28 Citations (Scopus)

Abstract

This brief presents a duty cycle corrector (DCC) using a binary search algorithm with successive approximation register (SAR). The proposed DCC consists of a duty-cycle detector, a duty-cycle adjuster, its controller and an output buffer. In order to achieve fast duty-correction with a small die area, a SAR-controller is exploited as a duty-correction controller. The proposed DCC circuit has been implemented and fabricated in a 0.13-μm CMOS process and occupies 0.048 mm 2. The measured duty-cycle error for the 50% duty-rate is below ±1% (or ±10 pS) within ±320 pS external input duty-cycle error. The duty of output signal is corrected only with 14 cycles. This DCC operates from 312.5 MHz to 1 GHz and dissipates 3.2 mW at 1 GHz.

Original languageEnglish
Article number5930339
Pages (from-to)1524-1528
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume20
Issue number8
DOIs
Publication statusPublished - 2012

Keywords

  • DRAM
  • Double data rate (DDR)
  • duty-cycle corrector (DCC)
  • successive approximation register (SAR) controller

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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