A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces

Hyunsu Park, Yoonjae Choi, Jincheol Sim, Jonghyuck Choi, Youngwook Kwon, Junyoung Song, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The bandwidth of parallel DRAM I/O has increased to meet big-data requirements. High bandwidth memory (HBM) interfaces use up to 1024 pins, and with an increased clock frequency, their power consumption has also increased [1]. Figure 28.5.1 shows four HBM interface approaches. Conventional HBM interfaces use a termination-less structure at the receiver to reduce power consumption. For higher data rates receiver-side termination can be used to improve signal integrity. However, this causes a large static current for long consecutive identical digits (CID). Di-code signaling can be used in HBM interfaces to reduce this static current. Nevertheless, there are still design constraints for conventional di-code interfaces, such as equalization, offset voltage, and series capacitor implementation constraints [2]. The series capacitor, specifically, causes frequency dependence and parasitic capacitance, which degrades its frequency range. In this paper, a capacitor-less and high-efficiency di-code transceiver using trans-impedance-amplifier (TIA) termination is implemented, as shown in Fig. 28.5.1. An adjustable inverter-based TIA is adopted for DC balancing the di-code signaling. A common-mode voltage calibration technique is proposed to minimize the static current during middle-level transmission. Several equalizing techniques for the di-code signaling are proposed to increase the sampling margin at the receiver and to maintain the common-mode voltage of di-code outputs. Also, an error correction circuit (ECC), based on di-code signaling, is implemented to reduce bit errors.

Original languageEnglish
Title of host publication2022 IEEE International Solid-State Circuits Conference, ISSCC 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages452-454
Number of pages3
ISBN (Electronic)9781665428002
DOIs
Publication statusPublished - 2022
Event2022 IEEE International Solid-State Circuits Conference, ISSCC 2022 - San Francisco, United States
Duration: 2022 Feb 202022 Feb 26

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume2022-February
ISSN (Print)0193-6530

Conference

Conference2022 IEEE International Solid-State Circuits Conference, ISSCC 2022
Country/TerritoryUnited States
CitySan Francisco
Period22/2/2022/2/26

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'A 0.385-pJ/bit 10-Gb/s TIA-Terminated Di-Code Transceiver with Edge-Delayed Equalization, ECC, and Mismatch Calibration for HBM Interfaces'. Together they form a unique fingerprint.

Cite this