A 0.4-mW, 4.7-ps resolution single-loop ΔΣ TDC using a half-delay time integrator

Chan Keun Kwon, Hoonki Kim, Jongsun Park, Soo Won Kim

Research output: Contribution to journalArticlepeer-review

5 Citations (Scopus)

Abstract

A compact, low-power, single-loop third-order delta-sigma (ΔΣ) time-to-digital converter (TDC) for time-mode signal processing is presented in this brief. In general, a high-resolution ΔΣ TDC requires a cascadable time integrator to increase the order of the loop filter. However, implementing the time integrator has been very challenging owing to the difficulty in storing time information. In this brief, we present a low-power half-delay time integrator, which is simply composed of two AND gates, a charge pump, and a comparator. The proposed time integrator can be easily cascaded (serially connected) to implement a loop filter with high-order noise shaping. The prototype TDC fabricated in 0.11-μm CMOS process occupies an active area of 0.11 mm2, consuming 0.4 mW from a 1.2 V supply. It achieves the dynamic range of 81 dB over a signal bandwidth of 50 kHz, and the resolution of 4.7 ps over a measurable range of 39.06 ns, which is half the clock period.

Original languageEnglish
Article number2438851
Pages (from-to)1184-1188
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume24
Issue number3
DOIs
Publication statusPublished - 2016 Mar

Keywords

  • Delta-sigma (ΔΣ) modulator
  • High resolution
  • Low power
  • Time-to-digital converter (TDC)

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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