A 0.5 v 10-bit 3 MS/s SAR ADC with adaptive-reset switching scheme and near-threshold voltage-optimized design technique

Jaegeun Song, Jaehun Jun, Jaehun Jun, Chulwoo Kim

Research output: Contribution to journalArticle

Abstract

This brief presents a 10-bit ultra-low power energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC). A new adaptive-reset switching scheme is proposed to reduce the switching energy of the capacitive digital-to-analog converter (CDAC). The proposed adaptive-reset switching scheme reduces the average switching energy of the CDAC by 90% compared to the conventional scheme without the common-mode voltage variation. In addition, the near-threshold voltage (NTV)-optimized digital library is adopted to alleviate the performance degradation in the ultra-low supply voltage while simultaneously increasing the energy efficiency. The NTV-optimized design technique is also introduced to the bootstrapped switch design to improve the linearity of the sample-and-hold circuit. The test chip is fabricated in a 65 nm CMOS, and its core area is 0.022 mm2. At a supply of 0.5 V and sampling speed of 3 MS/s, the SAR ADC achieves an ENOB of 8.78 bit and consumes 3.09 μW. The resultant Walden figure-of-merit (FoM) is 2.34 fJ/conv.-step.

Original languageEnglish
Article number8798982
Pages (from-to)1184-1188
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume67
Issue number7
DOIs
Publication statusPublished - 2020 Jul

Keywords

  • low power
  • near-threshold voltage
  • SAR ADC
  • switching algorithm
  • Ultra-low voltage

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A 0.5 v 10-bit 3 MS/s SAR ADC with adaptive-reset switching scheme and near-threshold voltage-optimized design technique'. Together they form a unique fingerprint.

  • Cite this