A 0.99-pJ/b 15-Gb/s Counter-Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS

Yoonjae Choi, Yeonho Lee, Hyunsu Park, Jonghyuck Choi, Jincheol Sim, Youngwook Kwon, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review


This brief presents a low-power counter-based adaptive equalizer that does not require additional power-hungry comparators for an equalizer adaptation loop. A pulse generator in the proposed equalizer obviates the need for additional error sampling comparators. Instead, it allows the receiver to utilize an output of a data decision comparator for the equalizer adaptation by generating a pulse that indicates whether the comparator makes a firm decision for the incoming data. A single comparator is shared by the data recovery path and equalizer adaptation loop. Consequently, the proposed counter-based equalizer achieves a low power dissipation owing to the reduced number of comparators. Fabricated in a 28-nm CMOS technology, the prototype receiver occupies an active area of 0.004 mm2 and consumes only 0.99-pJ/b at 15-Gb/s.

Original languageEnglish
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Publication statusAccepted/In press - 2021


  • Adaptive equalizer
  • Adaptive equalizers
  • Circuits and systems
  • Clocks
  • Decision feedback equalizers
  • Pulse generation
  • Receivers
  • Timing
  • continuous-time linear equalizer (CTLE)
  • counter-based adaptive equalizer
  • decision feedback equalizer (DFE)
  • receiver.

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


Dive into the research topics of 'A 0.99-pJ/b 15-Gb/s Counter-Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS'. Together they form a unique fingerprint.

Cite this