A 1-3.2 GHz 0.6 mW/GHz duty-cycle-corrector using bangbang duty-cyle-detector

Jincheol Sim, Hyunsu Park, Youngwook Kwon, Seongcheol Kim, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Duty cycle corrector (DCC) using a bang-bang duty cycle detector (BBDCD) correct a 1-3.2 GHz clock duty cycle. Because the accuracy of BBDCD determines the output clock duty cycle, to mitigate the offset of the BBDCD, an average codes method is used. The operating frequency is determined according to capacitance in the BBDCD for a wide frequency. A duty cycle adjuster (DCA) based on a 2-input NAND gate makes a clock with pulse width from the rising edge of the input clock to the falling edge of the digitally controlled delay line (DCDL) output. The IC is designed in CMOS 28nm process. The maximum duty cycle error of the DCC is 1.5 % at 3.2 GHz. The DCC consumes 1.92 mW at the maximum input frequency. The peak-to-peak jitter of the output clock is 12 ps.

Original languageEnglish
Title of host publication2021 IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728192017
DOIs
Publication statusPublished - 2021
Event53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021 - Daegu, Korea, Republic of
Duration: 2021 May 222021 May 28

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2021-May
ISSN (Print)0271-4310

Conference

Conference53rd IEEE International Symposium on Circuits and Systems, ISCAS 2021
Country/TerritoryKorea, Republic of
CityDaegu
Period21/5/2221/5/28

Keywords

  • Double data rate (DDR)
  • Duty cycle corrector (DCC)
  • Duty cycle detector (DCD)
  • Dynamic random access memory (DRAM)
  • Memory interface

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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