A 1 MS/s 9.15 ENOB Low-Power SAR ADC with Triple-Charge-Sharing Technique

Soonsung Ahn; Jaegeun Song; Chaegang Lim; Yohan Choi; Sooho Park; Yunsoo Park; Chulwoo Kim

doi:10.1109/ISOCC50952.2020.9332980

A 1 MS/s 9.15 ENOB Low-Power SAR ADC with Triple-Charge-Sharing Technique

Soonsung Ahn, Jaegeun Song, Chaegang Lim, Yohan Choi, Sooho Park, Yunsoo Park, Chulwoo Kim

School of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a 10-b 1 MS/s SAR ADC with a proposed triple-charge-sharing technique to reduce switching energy. The proposed technique uses an additional reservoir capacitor, which has 10% of total CDAC size, to recycle 56% of switching energy. The energy-saving efficiency of this technique is most noticeable in MSBs, so the number of the MSBs to apply the technique has been optimized. The prototype of the proposed SAR ADC is implemented in a 28 nm CMOS technology at 1 V supply voltage. Logic power is minimized with 0.4 V supply voltage. The proposed SAR ADC consumes 2.02 J.l W and achieves ENOB of 9.15, equivalent to a Walden FoM of 3.55 fJ/conversion-step.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference, ISOCC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1-2
Number of pages	2
ISBN (Electronic)	9781728183312
DOIs	https://doi.org/10.1109/ISOCC50952.2020.9332980
Publication status	Published - 2020 Oct 21
Event	17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of Duration: 2020 Oct 21 → 2020 Oct 24

Publication series

Name	Proceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference	17th International System-on-Chip Design Conference, ISOCC 2020
Country/Territory	Korea, Republic of
City	Yeosu
Period	20/10/21 → 20/10/24

Keywords

SAR ADC
TCS
charge sharing
low-power consumption
reservoir capacitor
triple-charge-sharing

ASJC Scopus subject areas

Energy Engineering and Power Technology
Electrical and Electronic Engineering
Instrumentation
Artificial Intelligence
Hardware and Architecture

Access to Document

10.1109/ISOCC50952.2020.9332980

Cite this

Ahn, S., Song, J., Lim, C., Choi, Y., Park, S., Park, Y., & Kim, C. (2020). A 1 MS/s 9.15 ENOB Low-Power SAR ADC with Triple-Charge-Sharing Technique. In Proceedings - International SoC Design Conference, ISOCC 2020 (pp. 1-2). [9332980] (Proceedings - International SoC Design Conference, ISOCC 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC50952.2020.9332980

A 1 MS/s 9.15 ENOB Low-Power SAR ADC with Triple-Charge-Sharing Technique. / Ahn, Soonsung; Song, Jaegeun; Lim, Chaegang et al.

Proceedings - International SoC Design Conference, ISOCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 1-2 9332980 (Proceedings - International SoC Design Conference, ISOCC 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ahn, S, Song, J, Lim, C, Choi, Y, Park, S, Park, Y & Kim, C 2020, A 1 MS/s 9.15 ENOB Low-Power SAR ADC with Triple-Charge-Sharing Technique. in Proceedings - International SoC Design Conference, ISOCC 2020., 9332980, Proceedings - International SoC Design Conference, ISOCC 2020, Institute of Electrical and Electronics Engineers Inc., pp. 1-2, 17th International System-on-Chip Design Conference, ISOCC 2020, Yeosu, Korea, Republic of, 20/10/21. https://doi.org/10.1109/ISOCC50952.2020.9332980

Ahn S, Song J, Lim C, Choi Y, Park S, Park Y et al. A 1 MS/s 9.15 ENOB Low-Power SAR ADC with Triple-Charge-Sharing Technique. In Proceedings - International SoC Design Conference, ISOCC 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 1-2. 9332980. (Proceedings - International SoC Design Conference, ISOCC 2020). doi: 10.1109/ISOCC50952.2020.9332980

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abstract = "This paper presents a 10-b 1 MS/s SAR ADC with a proposed triple-charge-sharing technique to reduce switching energy. The proposed technique uses an additional reservoir capacitor, which has 10% of total CDAC size, to recycle 56% of switching energy. The energy-saving efficiency of this technique is most noticeable in MSBs, so the number of the MSBs to apply the technique has been optimized. The prototype of the proposed SAR ADC is implemented in a 28 nm CMOS technology at 1 V supply voltage. Logic power is minimized with 0.4 V supply voltage. The proposed SAR ADC consumes 2.02 J.l W and achieves ENOB of 9.15, equivalent to a Walden FoM of 3.55 fJ/conversion-step. ",

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AB - This paper presents a 10-b 1 MS/s SAR ADC with a proposed triple-charge-sharing technique to reduce switching energy. The proposed technique uses an additional reservoir capacitor, which has 10% of total CDAC size, to recycle 56% of switching energy. The energy-saving efficiency of this technique is most noticeable in MSBs, so the number of the MSBs to apply the technique has been optimized. The prototype of the proposed SAR ADC is implemented in a 28 nm CMOS technology at 1 V supply voltage. Logic power is minimized with 0.4 V supply voltage. The proposed SAR ADC consumes 2.02 J.l W and achieves ENOB of 9.15, equivalent to a Walden FoM of 3.55 fJ/conversion-step.

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A 1 MS/s 9.15 ENOB Low-Power SAR ADC with Triple-Charge-Sharing Technique

Abstract

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Conference

Keywords

ASJC Scopus subject areas

Access to Document

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