A 1-V 10-Gb/s/pin Single-Ended Transceiver With Controllable Active-Inductor-Based Driver and Adaptively Calibrated Cascaded-Equalizer for Post-LPDDR4 Interfaces

Junyoung Song, Sewook Hwang, Hyun Woo Lee, Chulwoo Kim

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

A 1-V 10-Gb/s/pin single-ended transceiver with a controllable active inductor-based output driver and adaptively calibrated cascaded-equalizer with infinite impulse response and finite impulse response filters for a post-LPDDR4 interface in a 65-nm CMOS technology is proposed. The proposed cascaded-equalizer removes the received long-tail inter symbol interference with the help of an IIR filter while the coefficients for the cascaded-equalizer are adaptively calibrated. In addition, the received single-ended ground-terminated data are converted to the differential pair by the proposed input buffer using a calibrated reference voltage. In the transmitter (TX), an output driver with controllable active inductors is proposed to reduce both power consumption and design complexity. At the maximum operating data rate, the measured power efficiencies of TX and receiver are 1.16 and 3.02 pJ/b, respectively, excluding the power dissipation of internal phase locked loop. In addition, the overall active area is 0.0091 mm².

Original languageEnglish
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
DOIs
Publication statusAccepted/In press - 2017 Jul 27

Keywords

  • adaptive calibration.
  • Bandwidth
  • Decision feedback equalizers
  • Delays
  • DFE
  • DRAM interface
  • IIR filter
  • low-power DRAM
  • LPDDR
  • Market research
  • Power dissipation
  • Random access memory

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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