A 1.0-ns/1.0-V delay-locked loop with racing mode and countered CAS latency controller for DRAM interfaces

Hyun Woo Lee, Hoon Choi, Beom Ju Shin, Kyung Hoon Kim, Kyung Whan Kim, Jaeil Kim, Kwang Hyun Kim, Jong Ho Jung, Jae Hwan Kim, Eun Young Park, Jong Sam Kim, Jong Hwan Kim, Jin Hee Cho, Namgyu Rye, Jun Hyun Chun, Yunsaing Kim, Chulwoo Kim, Young Jung Choi, Byong Tae Chung

Research output: Contribution to journalArticlepeer-review

20 Citations (Scopus)

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Engineering & Materials Science