Abstract
This paper introduces the 10b 1MS/s SAR ADC with double sampling technique to reduce the power consumption. The SAR ADC is implemented in CMOS 1P8M 65nm technology and occupies 0.11um2. The maximum sampling rate is 1MS/s. The simulated SNDR and SFDR are 55.6dB and 62.7dB at 484kHz input frequency, respectively. The implemented data converter consumes 507uW with 1.2-V supply.
Original language | English |
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Pages (from-to) | 325-329 |
Number of pages | 5 |
Journal | Transactions of the Korean Institute of Electrical Engineers |
Volume | 60 |
Issue number | 2 |
DOIs | |
Publication status | Published - 2011 Feb |
Keywords
- 10b
- 1MS/s
- ADC
- Data converter
- Double sampling
- SAR
ASJC Scopus subject areas
- Electrical and Electronic Engineering