A 10bit 1MS/s 0.5mW SAR ADC with double sampling technique

Hokyu Lee, Moo Young Kim, Chulwoo Kim

Research output: Contribution to journalArticle

Abstract

This paper introduces the 10b 1MS/s SAR ADC with double sampling technique to reduce the power consumption. The SAR ADC is implemented in CMOS 1P8M 65nm technology and occupies 0.11um2. The maximum sampling rate is 1MS/s. The simulated SNDR and SFDR are 55.6dB and 62.7dB at 484kHz input frequency, respectively. The implemented data converter consumes 507uW with 1.2-V supply.

Original languageEnglish
Pages (from-to)325-329
Number of pages5
JournalTransactions of the Korean Institute of Electrical Engineers
Volume60
Issue number2
Publication statusPublished - 2011 Feb 1

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Electric power utilization

Keywords

  • 10b
  • 1MS/s
  • ADC
  • Data converter
  • Double sampling
  • SAR

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A 10bit 1MS/s 0.5mW SAR ADC with double sampling technique. / Lee, Hokyu; Kim, Moo Young; Kim, Chulwoo.

In: Transactions of the Korean Institute of Electrical Engineers, Vol. 60, No. 2, 01.02.2011, p. 325-329.

Research output: Contribution to journalArticle

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