A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC

Minyoung Song, Young Ho Kwak, Sunghoon Ahn, Wooseok Kim, Byeong Ha Park, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

An ADPLL with a piecewise linear calibrated hierarchical TDC is proposed to achieve a wide range of operation and a CPPLL is cascaded to filter out 1/f noise. A phase selectable divider is also proposed to divide the clock frequency while keeping the relative phase difference of output same as that of input. The cascaded hybrid PLL fabricated in 65nm CMOS process burns 17mW and occupies 0.4mm2. The measured jitters are 1.1nspp and 223.6ps rms, respectively with a multiplication factor of 1,024.

Original languageEnglish
Title of host publication2009 IEEE Custom Integrated Circuits Conference, CICC '09
Pages243-246
Number of pages4
DOIs
Publication statusPublished - 2009
Event2009 IEEE Custom Integrated Circuits Conference, CICC '09 - San Jose, CA, United States
Duration: 2009 Sep 132009 Sep 16

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

Other2009 IEEE Custom Integrated Circuits Conference, CICC '09
CountryUnited States
CitySan Jose, CA
Period09/9/1309/9/16

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC'. Together they form a unique fingerprint.

  • Cite this

    Song, M., Kwak, Y. H., Ahn, S., Kim, W., Park, B. H., & Kim, C. (2009). A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC. In 2009 IEEE Custom Integrated Circuits Conference, CICC '09 (pp. 243-246). [5280849] (Proceedings of the Custom Integrated Circuits Conference). https://doi.org/10.1109/CICC.2009.5280849