A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC

Minyoung Song, Young Ho Kwak, Sunghoon Ahn, Wooseok Kim, ByeongHa Park, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

An ADPLL with a piecewise linear calibrated hierarchical TDC is proposed to achieve a wide range of operation and a CPPLL is cascaded to filter out 1/f noise. A phase selectable divider is also proposed to divide the clock frequency while keeping the relative phase difference of output same as that of input. The cascaded hybrid PLL fabricated in 65nm CMOS process burns 17mW and occupies 0.4mm2. The measured jitters are 1.1nspp and 223.6ps rms, respectively with a multiplication factor of 1,024.

Original languageEnglish
Title of host publicationProceedings of the Custom Integrated Circuits Conference
Pages243-246
Number of pages4
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 IEEE Custom Integrated Circuits Conference, CICC '09 - San Jose, CA, United States
Duration: 2009 Sep 132009 Sep 16

Other

Other2009 IEEE Custom Integrated Circuits Conference, CICC '09
CountryUnited States
CitySan Jose, CA
Period09/9/1309/9/16

Fingerprint

Phase locked loops
Jitter
Clocks

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Song, M., Kwak, Y. H., Ahn, S., Kim, W., Park, B., & Kim, C. (2009). A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC. In Proceedings of the Custom Integrated Circuits Conference (pp. 243-246). [5280849] https://doi.org/10.1109/CICC.2009.5280849

A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC. / Song, Minyoung; Kwak, Young Ho; Ahn, Sunghoon; Kim, Wooseok; Park, ByeongHa; Kim, Chulwoo.

Proceedings of the Custom Integrated Circuits Conference. 2009. p. 243-246 5280849.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Song, M, Kwak, YH, Ahn, S, Kim, W, Park, B & Kim, C 2009, A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC. in Proceedings of the Custom Integrated Circuits Conference., 5280849, pp. 243-246, 2009 IEEE Custom Integrated Circuits Conference, CICC '09, San Jose, CA, United States, 09/9/13. https://doi.org/10.1109/CICC.2009.5280849
Song M, Kwak YH, Ahn S, Kim W, Park B, Kim C. A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC. In Proceedings of the Custom Integrated Circuits Conference. 2009. p. 243-246. 5280849 https://doi.org/10.1109/CICC.2009.5280849
Song, Minyoung ; Kwak, Young Ho ; Ahn, Sunghoon ; Kim, Wooseok ; Park, ByeongHa ; Kim, Chulwoo. / A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC. Proceedings of the Custom Integrated Circuits Conference. 2009. pp. 243-246
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