TY - GEN
T1 - A 10T SRAM Compute-In-Memory Macro with Analog MAC Operation and Time Domain Conversion
AU - Park, Hyunchul
AU - Lee, Kyeongho
AU - Park, Jongsun
N1 - Funding Information:
This work was supported in part by the National Research Foundation of Korea grant funded by the Korea government (NRF-2020R1A2C3014820), in part by the Institute of Information & communications Technology Planning & evaluation (IITP) grant founded by the Korea government (MIST) (No. 2021-0-00903-002, Development of Physical Vulnerability-based Attacks and its Countermeasures for Reliable On-Device Deep Learning Accelerator Design), and the EDA tool was supported by the IC Design Education Center(IDEC), Korea.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - This paper presents a novel 10T SRAM Compute-In-Memory (CIM) architecture that efficiently combines current-domain computation with time-domain analog readout. In the analog multiply and accumulation (MAC) computations of the proposed CIM, by weakening the bit-line (BL) discharge current, the MAC results are linearly formed, thus efficiently processing the binarized inputs and weights. In addition, to reduce the hardware cost of analog readout circuit, a time-domain based analog MAC conversion scheme using the current mirror-based voltage to time converter circuits and the flip-flop based time-to-digital converter (TDC) are employed. The hardware implementation results with 28nm CMOS process technology show that the proposed 128×64 SRAM CIM macro achieves a 1788-TOPS/W with 3.75ns delay at 0.9V. It also shows an 86.01% of inference accuracy using CIFAR-10 dataset with VGG-7 model. Compared with the previous works, the proposed SRAM CIM shows up to 4.43× improvement in TOPS/W.
AB - This paper presents a novel 10T SRAM Compute-In-Memory (CIM) architecture that efficiently combines current-domain computation with time-domain analog readout. In the analog multiply and accumulation (MAC) computations of the proposed CIM, by weakening the bit-line (BL) discharge current, the MAC results are linearly formed, thus efficiently processing the binarized inputs and weights. In addition, to reduce the hardware cost of analog readout circuit, a time-domain based analog MAC conversion scheme using the current mirror-based voltage to time converter circuits and the flip-flop based time-to-digital converter (TDC) are employed. The hardware implementation results with 28nm CMOS process technology show that the proposed 128×64 SRAM CIM macro achieves a 1788-TOPS/W with 3.75ns delay at 0.9V. It also shows an 86.01% of inference accuracy using CIFAR-10 dataset with VGG-7 model. Compared with the previous works, the proposed SRAM CIM shows up to 4.43× improvement in TOPS/W.
KW - compute in memory
KW - current domain compute
KW - memory
KW - time to digital converter
UR - http://www.scopus.com/inward/record.url?scp=85139047654&partnerID=8YFLogxK
U2 - 10.1109/AICAS54282.2022.9870016
DO - 10.1109/AICAS54282.2022.9870016
M3 - Conference contribution
AN - SCOPUS:85139047654
T3 - Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022
SP - 455
EP - 458
BT - Proceeding - IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022
Y2 - 13 June 2022 through 15 June 2022
ER -