A 12-bit 500-MS/s current steering CMOS DAC for high-speed PLC modems

A 12-bit 500-MS/s current steering digital-to-analog converter (DAC) for high-speed power line communication (PLC) modems is presented in this paper. The performance of current steering DAC is limited by the current cell mismatches and glitch problems caused by switching timing errors. In this paper, the current cell design procedure is presented to minimize random mismatches. Then, a new data-weighted averaging (DWA) technique with fewer glitches and low hardware complexity is proposed to compensate for the gradient mismatch. Spurious-free dynamic range (SFDR) improvement and low complexity are effectively achieved by employing both a row-column structure and a (CSA) structure as the floor plan of the proposed DAC. The proposed DAC is implemented in a standard 0.18-μm CMOS process with an active area of 2.445mm², which achieves a differential non linearity (DNL) of 0.25LSB and an integral non-linearity (INL) of 0.19LSB. Additionally, the SFDR increases by 13.2dB (on average) when employing the proposed DWA technique. The total power consumption of the proposed DAC is 176mW from a 1.8-V supply voltage.