A 120-MHz-1.8-GHz CMOS DLL-based clock generator for dynamic frequency scaling

Jin Han Kim, Young Ho Kwak, Mooyoung Kim, Soo Won Kim, Chulwoo Kim

Research output: Contribution to journalArticle

50 Citations (Scopus)

Abstract

A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-μm CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07 mm2 and has a peak-to-peak jitter of ±6.6 ps at 1.3 GHz.

Original languageEnglish
Article number1683899
Pages (from-to)2077-2082
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume41
Issue number9
DOIs
Publication statusPublished - 2006 Sep

Keywords

  • Clock generator
  • DLL-based frequency multiplication
  • Delay-locked loop (DLL)
  • Fast lock
  • Low jitter

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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