A 120-MHz-1.8-GHz CMOS DLL-based clock generator for dynamic frequency scaling

Jin Han Kim, Young Ho Kwak, Mooyoung Kim, Soo-Won Kim, Chulwoo Kim

Research output: Contribution to journalArticle

48 Citations (Scopus)

Abstract

A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-μm CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07 mm 2 and has a peak-to-peak jitter of ±6.6 ps at 1.3 GHz.

Original languageEnglish
Article number1683899
Pages (from-to)2077-2082
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Volume41
Issue number9
DOIs
Publication statusPublished - 2006 Sep 1

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Clocks
Dynamic frequency scaling
Jitter

Keywords

  • Clock generator
  • Delay-locked loop (DLL)
  • DLL-based frequency multiplication
  • Fast lock
  • Low jitter

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A 120-MHz-1.8-GHz CMOS DLL-based clock generator for dynamic frequency scaling. / Kim, Jin Han; Kwak, Young Ho; Kim, Mooyoung; Kim, Soo-Won; Kim, Chulwoo.

In: IEEE Journal of Solid-State Circuits, Vol. 41, No. 9, 1683899, 01.09.2006, p. 2077-2082.

Research output: Contribution to journalArticle

@article{1a8581c2311c4530b58e58fd3f47537c,
title = "A 120-MHz-1.8-GHz CMOS DLL-based clock generator for dynamic frequency scaling",
abstract = "A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-μm CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07 mm 2 and has a peak-to-peak jitter of ±6.6 ps at 1.3 GHz.",
keywords = "Clock generator, Delay-locked loop (DLL), DLL-based frequency multiplication, Fast lock, Low jitter",
author = "Kim, {Jin Han} and Kwak, {Young Ho} and Mooyoung Kim and Soo-Won Kim and Chulwoo Kim",
year = "2006",
month = "9",
day = "1",
doi = "10.1109/JSSC.2006.880609",
language = "English",
volume = "41",
pages = "2077--2082",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "9",

}

TY - JOUR

T1 - A 120-MHz-1.8-GHz CMOS DLL-based clock generator for dynamic frequency scaling

AU - Kim, Jin Han

AU - Kwak, Young Ho

AU - Kim, Mooyoung

AU - Kim, Soo-Won

AU - Kim, Chulwoo

PY - 2006/9/1

Y1 - 2006/9/1

N2 - A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-μm CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07 mm 2 and has a peak-to-peak jitter of ±6.6 ps at 1.3 GHz.

AB - A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-μm CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07 mm 2 and has a peak-to-peak jitter of ±6.6 ps at 1.3 GHz.

KW - Clock generator

KW - Delay-locked loop (DLL)

KW - DLL-based frequency multiplication

KW - Fast lock

KW - Low jitter

UR - http://www.scopus.com/inward/record.url?scp=33748340657&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33748340657&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2006.880609

DO - 10.1109/JSSC.2006.880609

M3 - Article

AN - SCOPUS:33748340657

VL - 41

SP - 2077

EP - 2082

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 9

M1 - 1683899

ER -