A 1.2GHz delayed clock generator for high-speed microprocessors

Inhwa Jung, Moo Young Kim, Chulwoo Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A 1.2GHz delayed clock generator capable of adjusting its clock phase according to input clock frequencies has been developed. It consists of a full-digital CMOS circuit that leads to a simple, robust, and portable IP. One-cycle lock time enables clock-on-demand circuit structures. The implemented delayed clock generator tile in 0.13um CMOS technology occupies only 0.004mm2 and operates at variable input frequencies ranging from 625MHz to 1.2GHz.

Original languageEnglish
Title of host publication2008 Asia and South Pacific Design Automation Conference, ASP-DAC
Pages95-96
Number of pages2
DOIs
Publication statusPublished - 2008 Aug 21
Event2008 Asia and South Pacific Design Automation Conference, ASP-DAC - Seoul, Korea, Republic of
Duration: 2008 Mar 212008 Mar 24

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other2008 Asia and South Pacific Design Automation Conference, ASP-DAC
CountryKorea, Republic of
CitySeoul
Period08/3/2108/3/24

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ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Jung, I., Kim, M. Y., & Kim, C. (2008). A 1.2GHz delayed clock generator for high-speed microprocessors. In 2008 Asia and South Pacific Design Automation Conference, ASP-DAC (pp. 95-96). [4484068] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2008.4484068