A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector

Hyun Woo Lee, Junyoung Song, Sang Ah Hyun, Seunggeun Baek, Yuri Lim, Jungwan Lee, Minsu Park, Haerang Choi, Changkyu Choi, Jinyoup Cha, Jaeil Kim, Hoon Choi, Seungwook Kwack, Yonggu Kang, Jongsam Kim, Junghoon Park, Jonghwan Kim, Jinhee Cho, Chulwoo Kim, Yunsaing KimJaejin Lee, Byongtae Chung, Sungjoo Hong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The demand for high-bandwidth memories is increasing with an increase in the need for high-performance systems. Wide-I/O memory and GDDR5 are two types of high-bandwidth memories. GDDR5 is more compatible than wide I/O for contemporary systems, such as graphics cards and game consoles. The datarate of GDDR5 has reached 7Gb/s/pin. However, the power consumption and cost have increased owing to high-performance-oriented designs, die penalties, and additional test costs. DDR4 is an alternative low-cost memory with high performance in the range of 2.4 to 3.2Gb/s/pin [1]. However it is difficult for DDR4 DRAM to raise the 3.2Gb/s/pin bin portion to lower the cost. In DRAMs, the standby power and self-refresh power are more important than the operating power because DRAMs are mainly in the standby or self-refresh mode in systems. As the operating speed increases, the data window is narrowed, and the jitter increases. Therefore, a duty-cycle corrector (DCC) is employed to increase the data window when the external clock duty cycle is distorted in GDDR5 [2]. The bang-bang jitter caused by the DCC is inevitable even if the external clock duty ratio is exactly 50%. Sometimes the DCC may distort the data window because of an internal DCC offset. This paper presents a GDDR5M (mainstream) memory for graphics cards and a small-outline dual-inline memory module) (SO-DIMM). The standby power is managed by the auto-sync mode. Additionally, the architecture of GDDR5M is similar to that of DDR4, and not GDDR5. The error-adaptive DCC can remove the initial duty-cycle offset automatically and remove the bang-bang jitter when the duty cycle of the external clock is not distorted.

Original languageEnglish
Title of host publication2014 IEEE International Solid-State Circuits Conference, ISSCC 2014 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages434-435
Number of pages2
ISBN (Print)9781479909186
DOIs
Publication statusPublished - 2014
Event2014 61st IEEE International Solid-State Circuits Conference, ISSCC 2014 - San Francisco, CA, United States
Duration: 2014 Feb 92014 Feb 13

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume57
ISSN (Print)0193-6530

Other

Other2014 61st IEEE International Solid-State Circuits Conference, ISSCC 2014
CountryUnited States
CitySan Francisco, CA
Period14/2/914/2/13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Lee, H. W., Song, J., Hyun, S. A., Baek, S., Lim, Y., Lee, J., Park, M., Choi, H., Choi, C., Cha, J., Kim, J., Choi, H., Kwack, S., Kang, Y., Kim, J., Park, J., Kim, J., Cho, J., Kim, C., ... Hong, S. (2014). A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. In 2014 IEEE International Solid-State Circuits Conference, ISSCC 2014 - Digest of Technical Papers (pp. 434-435). [6757502] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 57). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2014.6757502