Abstract
A wide-range fast-locking embedded clock receiver, which can provide a continuous data rate of 140 Mb/s to 1.82 Gb/s in a 0.25-μm CMOS process, is presented. A fast lock time of 7.5 μs and a small root-mean-square jitter of 15 ps are achieved by using the proposed frequency-band selection and frequency acquisition schemes, as well as a simple linear-phase detector. The implemented embedded clock receiver occupies 2.00 mm2 consumes currents of 44 and 137 mA at 140 Mb/s and 1.82 Gb/s, respectively, including input/output currents.
| Original language | English |
|---|---|
| Article number | 5282592 |
| Pages (from-to) | 773-777 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
| Volume | 56 |
| Issue number | 10 |
| DOIs | |
| Publication status | Published - 2009 Oct 1 |
Fingerprint
Keywords
- Clock and data recovery (CDR)
- Embedded clock
- Receiver
ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
A 140-Mb/s to 1.82-Gb/s continuous-rate embedded clock receiver for flat-panel displays. / Jung, Inhwa; Shin, Daejung; Kim, Taejin; Kim, Chulwoo.
In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 56, No. 10, 5282592, 01.10.2009, p. 773-777.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A 140-Mb/s to 1.82-Gb/s continuous-rate embedded clock receiver for flat-panel displays
AU - Jung, Inhwa
AU - Shin, Daejung
AU - Kim, Taejin
AU - Kim, Chulwoo
PY - 2009/10/1
Y1 - 2009/10/1
N2 - A wide-range fast-locking embedded clock receiver, which can provide a continuous data rate of 140 Mb/s to 1.82 Gb/s in a 0.25-μm CMOS process, is presented. A fast lock time of 7.5 μs and a small root-mean-square jitter of 15 ps are achieved by using the proposed frequency-band selection and frequency acquisition schemes, as well as a simple linear-phase detector. The implemented embedded clock receiver occupies 2.00 mm2 consumes currents of 44 and 137 mA at 140 Mb/s and 1.82 Gb/s, respectively, including input/output currents.
AB - A wide-range fast-locking embedded clock receiver, which can provide a continuous data rate of 140 Mb/s to 1.82 Gb/s in a 0.25-μm CMOS process, is presented. A fast lock time of 7.5 μs and a small root-mean-square jitter of 15 ps are achieved by using the proposed frequency-band selection and frequency acquisition schemes, as well as a simple linear-phase detector. The implemented embedded clock receiver occupies 2.00 mm2 consumes currents of 44 and 137 mA at 140 Mb/s and 1.82 Gb/s, respectively, including input/output currents.
KW - Clock and data recovery (CDR)
KW - Embedded clock
KW - Receiver
UR - http://www.scopus.com/inward/record.url?scp=79955727932&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79955727932&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2009.2030533
DO - 10.1109/TCSII.2009.2030533
M3 - Article
AN - SCOPUS:79955727932
VL - 56
SP - 773
EP - 777
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
SN - 1549-8328
IS - 10
M1 - 5282592
ER -