Abstract
This paper presents a design of a wide-range transceiver without an external reference clock. The self-biased and multi-band PLL with self-initialization technique is used for the wide-operating range of 140 Mb/s to 1.96 Gb/s and fast frequency acquisition time of 7.2 μs. A linear phase detector which has no dead-zone problem is proposed for a phase adjustment with a low-jitter performance. The rms jitter of the recovered clock is 11.4 ps at 70 MHz operation. The overall transceiver consumes 388 mW at 2.5 V supply and occupies 3.41 mm2 in a 0.25-μm 1P5M CMOS technology.
Original language | English |
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Article number | 5482002 |
Pages (from-to) | 1310-1315 |
Number of pages | 6 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 19 |
Issue number | 7 |
DOIs | |
Publication status | Published - 2011 Jul |
Keywords
- Clock and data recovery (CDR)
- embedded clock
- linear PD
- low voltage differential signaling (LVDS)
- low-jitter
- transceiver
- widerange
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering