A 140 Mb/s to 1.96 Gb/s referenceless transceiver with 7.2 μs frequency acquisition time

Inhwa Jung; Daejung Shin; Taejin Kim; Chulwoo Kim

doi:10.1109/TVLSI.2010.2047953

A 140 Mb/s to 1.96 Gb/s referenceless transceiver with 7.2 μs frequency acquisition time

Inhwa Jung, Daejung Shin, Taejin Kim, Chulwoo Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

This paper presents a design of a wide-range transceiver without an external reference clock. The self-biased and multi-band PLL with self-initialization technique is used for the wide-operating range of 140 Mb/s to 1.96 Gb/s and fast frequency acquisition time of 7.2 μs. A linear phase detector which has no dead-zone problem is proposed for a phase adjustment with a low-jitter performance. The rms jitter of the recovered clock is 11.4 ps at 70 MHz operation. The overall transceiver consumes 388 mW at 2.5 V supply and occupies 3.41 mm² in a 0.25-μm 1P5M CMOS technology.

Original language	English
Article number	5482002
Pages (from-to)	1310-1315
Number of pages	6
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	19
Issue number	7
DOIs	https://doi.org/10.1109/TVLSI.2010.2047953
Publication status	Published - 2011 Jul

Keywords

Clock and data recovery (CDR)
embedded clock
linear PD
low voltage differential signaling (LVDS)
low-jitter
transceiver
widerange

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/TVLSI.2010.2047953

Cite this

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title = "A 140 Mb/s to 1.96 Gb/s referenceless transceiver with 7.2 μs frequency acquisition time",

abstract = "This paper presents a design of a wide-range transceiver without an external reference clock. The self-biased and multi-band PLL with self-initialization technique is used for the wide-operating range of 140 Mb/s to 1.96 Gb/s and fast frequency acquisition time of 7.2 μs. A linear phase detector which has no dead-zone problem is proposed for a phase adjustment with a low-jitter performance. The rms jitter of the recovered clock is 11.4 ps at 70 MHz operation. The overall transceiver consumes 388 mW at 2.5 V supply and occupies 3.41 mm2 in a 0.25-μm 1P5M CMOS technology.",

keywords = "Clock and data recovery (CDR), embedded clock, linear PD, low voltage differential signaling (LVDS), low-jitter, transceiver, widerange",

author = "Inhwa Jung and Daejung Shin and Taejin Kim and Chulwoo Kim",

note = "Funding Information: Manuscript received February 25, 2009; revised July 02, 2009; accepted April 01, 2010. First published June 07, 2010; current version published June 24, 2011. This work was supported by the Korea Science and Engineering Foundation (KOSEF) Grant funded by the Korea Government (MEST) (R0A-2007-000-20059-0). The chip fabrication was supported by IC Design Education Center (IDEC) and the Korea Ministry of Knowledge Economy (MKE).",

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doi = "10.1109/TVLSI.2010.2047953",

language = "English",

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AU - Jung, Inhwa

AU - Shin, Daejung

AU - Kim, Taejin

AU - Kim, Chulwoo

N1 - Funding Information: Manuscript received February 25, 2009; revised July 02, 2009; accepted April 01, 2010. First published June 07, 2010; current version published June 24, 2011. This work was supported by the Korea Science and Engineering Foundation (KOSEF) Grant funded by the Korea Government (MEST) (R0A-2007-000-20059-0). The chip fabrication was supported by IC Design Education Center (IDEC) and the Korea Ministry of Knowledge Economy (MKE).

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AB - This paper presents a design of a wide-range transceiver without an external reference clock. The self-biased and multi-band PLL with self-initialization technique is used for the wide-operating range of 140 Mb/s to 1.96 Gb/s and fast frequency acquisition time of 7.2 μs. A linear phase detector which has no dead-zone problem is proposed for a phase adjustment with a low-jitter performance. The rms jitter of the recovered clock is 11.4 ps at 70 MHz operation. The overall transceiver consumes 388 mW at 2.5 V supply and occupies 3.41 mm2 in a 0.25-μm 1P5M CMOS technology.

KW - Clock and data recovery (CDR)

KW - embedded clock

KW - linear PD

KW - low voltage differential signaling (LVDS)

KW - low-jitter

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KW - widerange

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A 140 Mb/s to 1.96 Gb/s referenceless transceiver with 7.2 μs frequency acquisition time

Abstract

Keywords

ASJC Scopus subject areas

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