A 140 Mb/s to 1.96 Gb/s referenceless transceiver with 7.2 μs frequency acquisition time

Inhwa Jung, Daejung Shin, Taejin Kim, Chulwoo Kim

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

This paper presents a design of a wide-range transceiver without an external reference clock. The self-biased and multi-band PLL with self-initialization technique is used for the wide-operating range of 140 Mb/s to 1.96 Gb/s and fast frequency acquisition time of 7.2 μs. A linear phase detector which has no dead-zone problem is proposed for a phase adjustment with a low-jitter performance. The rms jitter of the recovered clock is 11.4 ps at 70 MHz operation. The overall transceiver consumes 388 mW at 2.5 V supply and occupies 3.41 mm2 in a 0.25-μm 1P5M CMOS technology.

Original languageEnglish
Article number5482002
Pages (from-to)1310-1315
Number of pages6
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume19
Issue number7
DOIs
Publication statusPublished - 2011 Jul

Keywords

  • Clock and data recovery (CDR)
  • embedded clock
  • linear PD
  • low voltage differential signaling (LVDS)
  • low-jitter
  • transceiver
  • widerange

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A 140 Mb/s to 1.96 Gb/s referenceless transceiver with 7.2 μs frequency acquisition time'. Together they form a unique fingerprint.

Cite this