A 140 Mb/s to 1.96 Gb/s referenceless transceiver with 7.2 μs frequency acquisition time

Inhwa Jung; Daejung Shin; Taejin Kim; Chulwoo Kim

doi:10.1109/TVLSI.2010.2047953

A 140 Mb/s to 1.96 Gb/s referenceless transceiver with 7.2 μs frequency acquisition time

Inhwa Jung, Daejung Shin, Taejin Kim, Chulwoo Kim

School of Electrical Engineering

Research output: Contribution to journal › Article

6 Citations (Scopus)

Abstract

This paper presents a design of a wide-range transceiver without an external reference clock. The self-biased and multi-band PLL with self-initialization technique is used for the wide-operating range of 140 Mb/s to 1.96 Gb/s and fast frequency acquisition time of 7.2 μs. A linear phase detector which has no dead-zone problem is proposed for a phase adjustment with a low-jitter performance. The rms jitter of the recovered clock is 11.4 ps at 70 MHz operation. The overall transceiver consumes 388 mW at 2.5 V supply and occupies 3.41 mm² in a 0.25-μm 1P5M CMOS technology.

Original language	English
Article number	5482002
Pages (from-to)	1310-1315
Number of pages	6
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	19
Issue number	7
DOIs	https://doi.org/10.1109/TVLSI.2010.2047953
Publication status	Published - 2011 Jul

Keywords

Clock and data recovery (CDR)
embedded clock
linear PD
low voltage differential signaling (LVDS)
low-jitter
transceiver
widerange

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/TVLSI.2010.2047953

Fingerprint Dive into the research topics of 'A 140 Mb/s to 1.96 Gb/s referenceless transceiver with 7.2 μs frequency acquisition time'. Together they form a unique fingerprint.

Cite this

@article{90bf33f6535d48229773a0b73004cc05,

title = "A 140 Mb/s to 1.96 Gb/s referenceless transceiver with 7.2 μs frequency acquisition time",

abstract = "This paper presents a design of a wide-range transceiver without an external reference clock. The self-biased and multi-band PLL with self-initialization technique is used for the wide-operating range of 140 Mb/s to 1.96 Gb/s and fast frequency acquisition time of 7.2 μs. A linear phase detector which has no dead-zone problem is proposed for a phase adjustment with a low-jitter performance. The rms jitter of the recovered clock is 11.4 ps at 70 MHz operation. The overall transceiver consumes 388 mW at 2.5 V supply and occupies 3.41 mm2 in a 0.25-μm 1P5M CMOS technology.",

keywords = "Clock and data recovery (CDR), embedded clock, linear PD, low voltage differential signaling (LVDS), low-jitter, transceiver, widerange",

author = "Inhwa Jung and Daejung Shin and Taejin Kim and Chulwoo Kim",

year = "2011",

month = jul,

doi = "10.1109/TVLSI.2010.2047953",

language = "English",

volume = "19",

pages = "1310--1315",

journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",

issn = "1063-8210",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "7",

}

TY - JOUR

T1 - A 140 Mb/s to 1.96 Gb/s referenceless transceiver with 7.2 μs frequency acquisition time

AU - Jung, Inhwa

AU - Shin, Daejung

AU - Kim, Taejin

AU - Kim, Chulwoo

PY - 2011/7

Y1 - 2011/7

N2 - This paper presents a design of a wide-range transceiver without an external reference clock. The self-biased and multi-band PLL with self-initialization technique is used for the wide-operating range of 140 Mb/s to 1.96 Gb/s and fast frequency acquisition time of 7.2 μs. A linear phase detector which has no dead-zone problem is proposed for a phase adjustment with a low-jitter performance. The rms jitter of the recovered clock is 11.4 ps at 70 MHz operation. The overall transceiver consumes 388 mW at 2.5 V supply and occupies 3.41 mm2 in a 0.25-μm 1P5M CMOS technology.

AB - This paper presents a design of a wide-range transceiver without an external reference clock. The self-biased and multi-band PLL with self-initialization technique is used for the wide-operating range of 140 Mb/s to 1.96 Gb/s and fast frequency acquisition time of 7.2 μs. A linear phase detector which has no dead-zone problem is proposed for a phase adjustment with a low-jitter performance. The rms jitter of the recovered clock is 11.4 ps at 70 MHz operation. The overall transceiver consumes 388 mW at 2.5 V supply and occupies 3.41 mm2 in a 0.25-μm 1P5M CMOS technology.

KW - Clock and data recovery (CDR)

KW - embedded clock

KW - linear PD

KW - low voltage differential signaling (LVDS)

KW - low-jitter

KW - transceiver

KW - widerange

UR - http://www.scopus.com/inward/record.url?scp=79959699201&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79959699201&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2010.2047953

DO - 10.1109/TVLSI.2010.2047953

M3 - Article

AN - SCOPUS:79959699201

VL - 19

SP - 1310

EP - 1315

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 7

M1 - 5482002

ER -