A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique with 1-Tap Latched DFE for DRAM Interfaces

Seongcheol Kim, Jincheol Sim, Hyunsu Park, Yoonjae Choi, Jonghyuck Choi, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

Abstract

This brief presents a single-ended (SE) receiver (RX) with a self-referenced (SR) technique using sample and hold (S&H) circuits. The proposed RX does not require a reference voltage (VREF) for data recovery by comparing the present data with previous data. The RX was implemented as half-rate architecture to halve the clock frequency and facilitate the S&H operation. Moreover, the proposed decision feedback equalizer (DFE) is suitable for SR RX and improves the reliability of RX by eliminating inter-symbol interference (ISI). The prototype RX, fabricated using 28-nm CMOS technology, occupies a 0.0016 mm2 active area. The measurement result of the proposed RX achieves a bit-error-rate (BER) under 10-12 with a 15-Gb/s data rate in a 17-inch PCB FR4 channel. The RX consumes 13.56 mW of power and has a power efficiency of 0.90 pJ/bit.

Original languageEnglish
Pages (from-to)1
Number of pages1
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
DOIs
Publication statusAccepted/In press - 2022

Keywords

  • Clocks
  • DRAM interface
  • Decision feedback equalizer
  • Decision feedback equalizers
  • Random access memory
  • Receivers
  • Robustness
  • Self-referenced
  • Single-ended receiver
  • Timing
  • Voltage

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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