A 1.62 Gb/s-2.7 Gb/s referenceless transceiver for displayport v1.1a with weighted phase and frequency detection

Junyoung Song, Inhwa Jung, Minyoung Song, Young Ho Kwak, Sewook Hwang, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

25 Citations (Scopus)

Abstract

This paper proposes a 2.7 Gb/s referenceless transceiver with weighted PFD for frequency detection of random signals. A single loop referenceless CDR is also proposed to overcome the disadvantages of a dual loop CDR. The ANSI 8b/10b encoder & decoder with the scrambler, the serializer & de-serializer, and the output driver with pre-emphasis are included in the proposed transceiver architecture for DisplayPort v1.1a. The jitter of the generated clock at the Tx PLL is 3.28 psrms at 2.7 Gb/s with 1.2 V supply. The eye opening of the transmitter output with 3 m cable is 0.54 UI. The measured jitter of the recovered clock at the CDR is 1.57 psrms, and BER is less than 10-12. The receiver consumes 23 mW at 2.7 Gb/s with 1.2 V supply. The CDR core and transceiver occupy 0.07 mm2 and 0.94 mm2, respectively, in a 0.13 μm 1P8M CMOS process.

Original languageEnglish
Article number6298054
Pages (from-to)268-278
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume60
Issue number2
DOIs
Publication statusPublished - 2013

Keywords

  • Clock and data recovery
  • phase and frequency detection
  • phase detection
  • referenceless transceiver

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'A 1.62 Gb/s-2.7 Gb/s referenceless transceiver for displayport v1.1a with weighted phase and frequency detection'. Together they form a unique fingerprint.

Cite this