A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology

Hyun Woo Lee, Ki Han Kim, Young Kyoung Choi, Ju Hwan Shon, Nak Kyu Park, Kwan Weon Kim, Chulwoo Kim, Young Jung Choi, Byong Tae Chung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

DRAM's process technology has been scaled down rapidly and the size of the wafer has reached 300mm. Despite being fabricated on the same wafer, two chips may have very different characteristics if the one is from the center and the other is from the edge of wafer. Therefore, the process skew reduction is becoming more important as the process is scaled down under 100nm. The dynamic voltage scaling scheme (DVS) has already won huge popularity in mobile applications with limited battery life. Various dynamic voltage scaling techniques for μ-processors have also been developed during the last decade [1]. However, selection of the power supply voltage for DRAM is dictated by the application or the worst process skew that guarantees the performance of DRAM. This paper proposes a self-dynamic voltage scaling (SDVS) technique for DRAM to overcome the process variation and reduce the power consumption according to the operating frequency.

Original languageEnglish
Title of host publicationDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Pages502-503
Number of pages2
DOIs
Publication statusPublished - 2011 May 12
Event2011 IEEE International Solid-State Circuits Conference, ISSCC 2011 - San Francisco, CA, United States
Duration: 2011 Feb 202011 Feb 24

Other

Other2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
CountryUnited States
CitySan Francisco, CA
Period11/2/2011/2/24

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Dynamic random access storage
Electric power utilization
Voltage scaling
Electric potential

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Lee, H. W., Kim, K. H., Choi, Y. K., Shon, J. H., Park, N. K., Kim, K. W., ... Chung, B. T. (2011). A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference (pp. 502-503). [5746416] https://doi.org/10.1109/ISSCC.2011.5746416

A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology. / Lee, Hyun Woo; Kim, Ki Han; Choi, Young Kyoung; Shon, Ju Hwan; Park, Nak Kyu; Kim, Kwan Weon; Kim, Chulwoo; Choi, Young Jung; Chung, Byong Tae.

Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2011. p. 502-503 5746416.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lee, HW, Kim, KH, Choi, YK, Shon, JH, Park, NK, Kim, KW, Kim, C, Choi, YJ & Chung, BT 2011, A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology. in Digest of Technical Papers - IEEE International Solid-State Circuits Conference., 5746416, pp. 502-503, 2011 IEEE International Solid-State Circuits Conference, ISSCC 2011, San Francisco, CA, United States, 11/2/20. https://doi.org/10.1109/ISSCC.2011.5746416
Lee HW, Kim KH, Choi YK, Shon JH, Park NK, Kim KW et al. A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology. In Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2011. p. 502-503. 5746416 https://doi.org/10.1109/ISSCC.2011.5746416
Lee, Hyun Woo ; Kim, Ki Han ; Choi, Young Kyoung ; Shon, Ju Hwan ; Park, Nak Kyu ; Kim, Kwan Weon ; Kim, Chulwoo ; Choi, Young Jung ; Chung, Byong Tae. / A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology. Digest of Technical Papers - IEEE International Solid-State Circuits Conference. 2011. pp. 502-503
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