A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM

Jungtaek You, Junyoung Song, Chulwoo Kim

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This brief proposes a data-dependent swing-limited on-chip signaling for single-ended global I/O in the SDRAM in a 0.13-μm CMOS technology. The SDRAM has multiple global I/O lines for sending and receiving data, which results in a large delay deviation owing to the multi-drop bus topology and a large RC load. Minimizing the delay and its deviation improves the speed of the SDRAM. With the proposed technique, the maximum speed is 2 Gb/s/ch, which is increased by more than 120% under the same channel condition. The power consumption is also reduced compared to that of the conventional scheme; the energy efficiency is 104 fJ/b/mm, respectively.

Original languageEnglish
Article number7279097
Pages (from-to)1207-1211
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume64
Issue number10
DOIs
Publication statusPublished - 2017 Oct 1

Fingerprint

Energy efficiency
Electric power utilization
Topology

Keywords

  • Memory
  • on-chip signaling
  • single-ended global I/O
  • synchronous dynamic random access memory (SDRAM)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM. / You, Jungtaek; Song, Junyoung; Kim, Chulwoo.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 64, No. 10, 7279097, 01.10.2017, p. 1207-1211.

Research output: Contribution to journalArticle

@article{86798a71acc644e6b5e590a523be45d6,
title = "A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM",
abstract = "This brief proposes a data-dependent swing-limited on-chip signaling for single-ended global I/O in the SDRAM in a 0.13-μm CMOS technology. The SDRAM has multiple global I/O lines for sending and receiving data, which results in a large delay deviation owing to the multi-drop bus topology and a large RC load. Minimizing the delay and its deviation improves the speed of the SDRAM. With the proposed technique, the maximum speed is 2 Gb/s/ch, which is increased by more than 120{\%} under the same channel condition. The power consumption is also reduced compared to that of the conventional scheme; the energy efficiency is 104 fJ/b/mm, respectively.",
keywords = "Memory, on-chip signaling, single-ended global I/O, synchronous dynamic random access memory (SDRAM)",
author = "Jungtaek You and Junyoung Song and Chulwoo Kim",
year = "2017",
month = "10",
day = "1",
doi = "10.1109/TCSII.2015.2483158",
language = "English",
volume = "64",
pages = "1207--1211",
journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",
issn = "1549-8328",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "10",

}

TY - JOUR

T1 - A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM

AU - You, Jungtaek

AU - Song, Junyoung

AU - Kim, Chulwoo

PY - 2017/10/1

Y1 - 2017/10/1

N2 - This brief proposes a data-dependent swing-limited on-chip signaling for single-ended global I/O in the SDRAM in a 0.13-μm CMOS technology. The SDRAM has multiple global I/O lines for sending and receiving data, which results in a large delay deviation owing to the multi-drop bus topology and a large RC load. Minimizing the delay and its deviation improves the speed of the SDRAM. With the proposed technique, the maximum speed is 2 Gb/s/ch, which is increased by more than 120% under the same channel condition. The power consumption is also reduced compared to that of the conventional scheme; the energy efficiency is 104 fJ/b/mm, respectively.

AB - This brief proposes a data-dependent swing-limited on-chip signaling for single-ended global I/O in the SDRAM in a 0.13-μm CMOS technology. The SDRAM has multiple global I/O lines for sending and receiving data, which results in a large delay deviation owing to the multi-drop bus topology and a large RC load. Minimizing the delay and its deviation improves the speed of the SDRAM. With the proposed technique, the maximum speed is 2 Gb/s/ch, which is increased by more than 120% under the same channel condition. The power consumption is also reduced compared to that of the conventional scheme; the energy efficiency is 104 fJ/b/mm, respectively.

KW - Memory

KW - on-chip signaling

KW - single-ended global I/O

KW - synchronous dynamic random access memory (SDRAM)

UR - http://www.scopus.com/inward/record.url?scp=85030833653&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85030833653&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2015.2483158

DO - 10.1109/TCSII.2015.2483158

M3 - Article

AN - SCOPUS:85030833653

VL - 64

SP - 1207

EP - 1211

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

SN - 1549-8328

IS - 10

M1 - 7279097

ER -