A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM

Jungtaek You; Junyoung Song; Chulwoo Kim

doi:10.1109/TCSII.2015.2483158

A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM

Jungtaek You, Junyoung Song, Chulwoo Kim

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

This brief proposes a data-dependent swing-limited on-chip signaling for single-ended global I/O in the SDRAM in a 0.13-μm CMOS technology. The SDRAM has multiple global I/O lines for sending and receiving data, which results in a large delay deviation owing to the multi-drop bus topology and a large RC load. Minimizing the delay and its deviation improves the speed of the SDRAM. With the proposed technique, the maximum speed is 2 Gb/s/ch, which is increased by more than 120% under the same channel condition. The power consumption is also reduced compared to that of the conventional scheme; the energy efficiency is 104 fJ/b/mm, respectively.

Original language	English
Article number	7279097
Pages (from-to)	1207-1211
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	64
Issue number	10
DOIs	https://doi.org/10.1109/TCSII.2015.2483158
Publication status	Published - 2017 Oct

Keywords

Memory
on-chip signaling
single-ended global I/O
synchronous dynamic random access memory (SDRAM)

ASJC Scopus subject areas

Electrical and Electronic Engineering

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/TCSII.2015.2483158

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@article{86798a71acc644e6b5e590a523be45d6,

title = "A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM",

abstract = "This brief proposes a data-dependent swing-limited on-chip signaling for single-ended global I/O in the SDRAM in a 0.13-μm CMOS technology. The SDRAM has multiple global I/O lines for sending and receiving data, which results in a large delay deviation owing to the multi-drop bus topology and a large RC load. Minimizing the delay and its deviation improves the speed of the SDRAM. With the proposed technique, the maximum speed is 2 Gb/s/ch, which is increased by more than 120% under the same channel condition. The power consumption is also reduced compared to that of the conventional scheme; the energy efficiency is 104 fJ/b/mm, respectively.",

keywords = "Memory, on-chip signaling, single-ended global I/O, synchronous dynamic random access memory (SDRAM)",

author = "Jungtaek You and Junyoung Song and Chulwoo Kim",

note = "Funding Information: Manuscript received April 23, 2015; revised July 1, 2015 and August 18, 2015; accepted September 5, 2015. Date of publication September 28, 2015; date of current version September 25, 2017. This research was supported by the National Research Foundation of Korea through the Korea Government within the Ministry of Education, Science and Technology under Grant NRF-2011-0020128; the fabrication was supported by Multi-Project Wafer of IC Design Education Center. This brief was recommended by Associate Editor Y.-B. Kim. Publisher Copyright: {\textcopyright} 2015 IEEE.",

year = "2017",

month = oct,

doi = "10.1109/TCSII.2015.2483158",

language = "English",

volume = "64",

pages = "1207--1211",

journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",

issn = "1549-8328",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "10",

}

TY - JOUR

T1 - A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM

AU - You, Jungtaek

AU - Song, Junyoung

AU - Kim, Chulwoo

N1 - Funding Information: Manuscript received April 23, 2015; revised July 1, 2015 and August 18, 2015; accepted September 5, 2015. Date of publication September 28, 2015; date of current version September 25, 2017. This research was supported by the National Research Foundation of Korea through the Korea Government within the Ministry of Education, Science and Technology under Grant NRF-2011-0020128; the fabrication was supported by Multi-Project Wafer of IC Design Education Center. This brief was recommended by Associate Editor Y.-B. Kim. Publisher Copyright: © 2015 IEEE.

PY - 2017/10

Y1 - 2017/10

N2 - This brief proposes a data-dependent swing-limited on-chip signaling for single-ended global I/O in the SDRAM in a 0.13-μm CMOS technology. The SDRAM has multiple global I/O lines for sending and receiving data, which results in a large delay deviation owing to the multi-drop bus topology and a large RC load. Minimizing the delay and its deviation improves the speed of the SDRAM. With the proposed technique, the maximum speed is 2 Gb/s/ch, which is increased by more than 120% under the same channel condition. The power consumption is also reduced compared to that of the conventional scheme; the energy efficiency is 104 fJ/b/mm, respectively.

AB - This brief proposes a data-dependent swing-limited on-chip signaling for single-ended global I/O in the SDRAM in a 0.13-μm CMOS technology. The SDRAM has multiple global I/O lines for sending and receiving data, which results in a large delay deviation owing to the multi-drop bus topology and a large RC load. Minimizing the delay and its deviation improves the speed of the SDRAM. With the proposed technique, the maximum speed is 2 Gb/s/ch, which is increased by more than 120% under the same channel condition. The power consumption is also reduced compared to that of the conventional scheme; the energy efficiency is 104 fJ/b/mm, respectively.

KW - Memory

KW - on-chip signaling

KW - single-ended global I/O

KW - synchronous dynamic random access memory (SDRAM)

UR - http://www.scopus.com/inward/record.url?scp=85030833653&partnerID=8YFLogxK

U2 - 10.1109/TCSII.2015.2483158

DO - 10.1109/TCSII.2015.2483158

M3 - Article

AN - SCOPUS:85030833653

SN - 1549-8328

VL - 64

SP - 1207

EP - 1211

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

IS - 10

M1 - 7279097

ER -

A 2-Gb/s/ch Data-Dependent Swing-Limited On-Chip Signaling for Single-Ended Global I/O in SDRAM

Abstract

Keywords

ASJC Scopus subject areas

UN SDGs

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