A 20 Gb/s clock and data recovery with a ping-pong delay line for unlimited phase shifting in 65 nm CMOS process

Young Ho Kwak, Yongtae Kim, Sewook Hwang, Chulwoo Kim

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

This paper describes a 20 Gb/s receiver with a DLL-based CDR, which uses a proposed Ping-Pong delay line (PPDL) in order to ameliorate the limited operating range problem of the DLL. The unlimited phase shifting algorithm with the PPDL extends the tracking range of the DLL-based CDR. The PPDL correlates two variable delay lines and swaps each other whenever one of them reaches its operational limit. The chip occupies 0.24 mm2 in 65 nm CMOS process. The power efficiency of the data transfer is 8.46 mW/Gb/s. The measured jitter of the 5 GHz clock is 1.125 psrms and the data eye opening is 0.613UI.

Original languageEnglish
Article number6419863
Pages (from-to)303-313
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume60
Issue number2
DOIs
Publication statusPublished - 2013 Feb 11

Fingerprint

Electric delay lines
Clocks
Recovery
Data transfer
Jitter

Keywords

  • 65 nm CMOS process
  • CDR
  • DLL
  • infinite phase shift
  • oversampling
  • ping-pong delay line
  • PLL
  • receiver
  • voltage regulator
  • wide tracking range

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A 20 Gb/s clock and data recovery with a ping-pong delay line for unlimited phase shifting in 65 nm CMOS process. / Kwak, Young Ho; Kim, Yongtae; Hwang, Sewook; Kim, Chulwoo.

In: IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 60, No. 2, 6419863, 11.02.2013, p. 303-313.

Research output: Contribution to journalArticle

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