A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop with Delay-Cell-Less TDC

Minyoung Song, Inhwa Jung, Sudhakar Pamarti, Chulwoo Kim

Research output: Contribution to journalArticle

16 Citations (Scopus)

Abstract

An all-digital phase locked loop (ADPLL) with a proposed time-to-digital converter (TDC) which has no delay cell is designed by the 0.13-\mu{\rm m} CMOS process. The delay-cell-less TDC (DLTDC) that can suppress device noises and PVT mismatches is essential for wider bandwidth operations. Moreover, sub-gate TDC resolution can be achieved with the proposed DLTDC. A ring-VCO based digitally-controlled oscillator (DCO) which reduces 1/f noise is also proposed to enhance noise performance. The 2 MHz BW ADPLL which occupies 0.42 {\rm mm}2 consumes 12 mA and its measured jitter is 4 {\rm ps} \rm rms at 2.4 GHz.

Original languageEnglish
Article number6585805
Pages (from-to)3145-3151
Number of pages7
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume60
Issue number12
DOIs
Publication statusPublished - 2013 Dec 1

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Phase locked loops
Bandwidth
Variable frequency oscillators
Jitter

Keywords

  • All-digital PLL (ADPLL)
  • delay-cell-less TDC
  • low noise VCO
  • phase-locked loop (PLL)
  • time-to-digital converter (TDC)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop with Delay-Cell-Less TDC. / Song, Minyoung; Jung, Inhwa; Pamarti, Sudhakar; Kim, Chulwoo.

In: IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 60, No. 12, 6585805, 01.12.2013, p. 3145-3151.

Research output: Contribution to journalArticle

@article{ee3cf15ddd224350b44a782938df9a48,
title = "A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop with Delay-Cell-Less TDC",
abstract = "An all-digital phase locked loop (ADPLL) with a proposed time-to-digital converter (TDC) which has no delay cell is designed by the 0.13-\mu{\rm m} CMOS process. The delay-cell-less TDC (DLTDC) that can suppress device noises and PVT mismatches is essential for wider bandwidth operations. Moreover, sub-gate TDC resolution can be achieved with the proposed DLTDC. A ring-VCO based digitally-controlled oscillator (DCO) which reduces 1/f noise is also proposed to enhance noise performance. The 2 MHz BW ADPLL which occupies 0.42 {\rm mm}2 consumes 12 mA and its measured jitter is 4 {\rm ps} \rm rms at 2.4 GHz.",
keywords = "All-digital PLL (ADPLL), delay-cell-less TDC, low noise VCO, phase-locked loop (PLL), time-to-digital converter (TDC)",
author = "Minyoung Song and Inhwa Jung and Sudhakar Pamarti and Chulwoo Kim",
year = "2013",
month = "12",
day = "1",
doi = "10.1109/TCSI.2013.2265975",
language = "English",
volume = "60",
pages = "3145--3151",
journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",
issn = "1549-8328",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "12",

}

TY - JOUR

T1 - A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop with Delay-Cell-Less TDC

AU - Song, Minyoung

AU - Jung, Inhwa

AU - Pamarti, Sudhakar

AU - Kim, Chulwoo

PY - 2013/12/1

Y1 - 2013/12/1

N2 - An all-digital phase locked loop (ADPLL) with a proposed time-to-digital converter (TDC) which has no delay cell is designed by the 0.13-\mu{\rm m} CMOS process. The delay-cell-less TDC (DLTDC) that can suppress device noises and PVT mismatches is essential for wider bandwidth operations. Moreover, sub-gate TDC resolution can be achieved with the proposed DLTDC. A ring-VCO based digitally-controlled oscillator (DCO) which reduces 1/f noise is also proposed to enhance noise performance. The 2 MHz BW ADPLL which occupies 0.42 {\rm mm}2 consumes 12 mA and its measured jitter is 4 {\rm ps} \rm rms at 2.4 GHz.

AB - An all-digital phase locked loop (ADPLL) with a proposed time-to-digital converter (TDC) which has no delay cell is designed by the 0.13-\mu{\rm m} CMOS process. The delay-cell-less TDC (DLTDC) that can suppress device noises and PVT mismatches is essential for wider bandwidth operations. Moreover, sub-gate TDC resolution can be achieved with the proposed DLTDC. A ring-VCO based digitally-controlled oscillator (DCO) which reduces 1/f noise is also proposed to enhance noise performance. The 2 MHz BW ADPLL which occupies 0.42 {\rm mm}2 consumes 12 mA and its measured jitter is 4 {\rm ps} \rm rms at 2.4 GHz.

KW - All-digital PLL (ADPLL)

KW - delay-cell-less TDC

KW - low noise VCO

KW - phase-locked loop (PLL)

KW - time-to-digital converter (TDC)

UR - http://www.scopus.com/inward/record.url?scp=84890075991&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84890075991&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2013.2265975

DO - 10.1109/TCSI.2013.2265975

M3 - Article

AN - SCOPUS:84890075991

VL - 60

SP - 3145

EP - 3151

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

SN - 1549-8328

IS - 12

M1 - 6585805

ER -