A 2.4 GHz 0.1-Fref-Bandwidth All-Digital Phase-Locked Loop with Delay-Cell-Less TDC

Minyoung Song, Inhwa Jung, Sudhakar Pamarti, Chulwoo Kim

Research output: Contribution to journalArticle

17 Citations (Scopus)


An all-digital phase locked loop (ADPLL) with a proposed time-to-digital converter (TDC) which has no delay cell is designed by the 0.13-\mu{\rm m} CMOS process. The delay-cell-less TDC (DLTDC) that can suppress device noises and PVT mismatches is essential for wider bandwidth operations. Moreover, sub-gate TDC resolution can be achieved with the proposed DLTDC. A ring-VCO based digitally-controlled oscillator (DCO) which reduces 1/f noise is also proposed to enhance noise performance. The 2 MHz BW ADPLL which occupies 0.42 {\rm mm}2 consumes 12 mA and its measured jitter is 4 {\rm ps} \rm rms at 2.4 GHz.

Original languageEnglish
Article number6585805
Pages (from-to)3145-3151
Number of pages7
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number12
Publication statusPublished - 2013 Dec 1



  • All-digital PLL (ADPLL)
  • delay-cell-less TDC
  • low noise VCO
  • phase-locked loop (PLL)
  • time-to-digital converter (TDC)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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