A 25 Gb/s Wireline Receiver With Feedforward and Feedback Equalizers at Analog Front-End

An important issue in wireline receivers (RX) is minimizing the area and power consumption while overcoming the channel attenuation with an equalizer. The greater the compensation for channel loss at the analog front end (AFE) of the RX, the lower the number of decision feedback equalizer (DFE) taps. Power dissipation and area can be reduced by reducing the number of DFE taps. This brief presents a technology that compensates for the channel loss with the proposed AFE based on a two-stage continuous-time linear equalizer (CTLE), low and high bandwidth amplifiers, and a gain controller. It sufficiently reduces the DC gain and increases the peak gain of the AFE by using a feedforward equalizer (FFEQ) and feedback equalizer (FBEQ). These equalizers result in an increase in the difference between the peak and DC gains and the gain difference at the fundamental frequency (f0) and 2nd subharmonic frequency (f1/2). The IC is fabricated in a 28 nm CMOS process, and the proposed architecture yields a BER less than 10-12 at 25.8 dB channel attenuation. At 25 Gb/s, the area and power efficiency of the proposed AFE are 1.19 pJ/bit and 0.01 mm2, respectively.