A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit with Clock Frequency Multiplier

Ja Young Kim, Junyoung Song, Jungtaek You, Sewook Hwang, Sang Geun Bae, Chulwoo Kim

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)

Abstract

This brief describes the design and implementation of a 250-Mb/s to 6-Gb/s single-loop referenceless clock and data recovery circuit. The clock frequency multiplier and the referenceless frequency acquisition circuit are used to cover a wide-range data rate. The clock frequency multiplier is proposed to generate the 6-GHz clock with low jitter. In addition, the voltage-controlled oscillator operates at 1/5-rate frequency of the sampling clock, which has a merit of low power consumption. The proposed circuit achieves 9.56-ps rms jitter, consumes 13.2 mW at 6 Gb/s, and occupies 0.0944 mm2 in a 65-nm CMOS technology.

Original languageEnglish
Pages (from-to)650-654
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume64
Issue number6
DOIs
Publication statusPublished - 2017 Jun

Keywords

  • Clock and data recovery circuit (CDR)
  • clock frequency multiplier
  • referenceless
  • referenceless frequency acquisition circuit (RFAC)
  • single loop

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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