Abstract
This paper describes the design and the implementation of a 250Mb/s to 6Gb/s single-loop reference-less clock and data recovery circuit. The clock frequency multiplier and the reference-less frequency acquisition circuit are used to cover a wide-range data rate. The clock frequency multiplier is proposed to generate the 6GHz clock with low jitter. Also, VCO operates at 1/5-rate frequency of the sampling clock, which has a merit of low power consumption. The proposed circuit achieves 9.56ps RMS jitter, consumes 13.2mW at 6Gb/s and occupies 0.0944mm2 in a 65-nm CMOS technology.
Original language | English |
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Article number | 7337379 |
Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
Volume | PP |
Issue number | 99 |
DOIs | |
Publication status | Published - 2015 |
Keywords
- Clock and data recovery circuit (CDR)
- Clock frequency multiplier
- Reference-less
- Single-loop
- The reference-less frequency acquisition circuit (RFAC)
ASJC Scopus subject areas
- Electrical and Electronic Engineering