A 250Mb/s to 6Gb/s reference-less clock and data recovery circuit with clock frequency multiplier

Ja Young Kim, Junyoung Song, Jungtaek You, Sewook Hwang, Sang Geun Bae, Chulwoo Kim

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

This paper describes the design and the implementation of a 250Mb/s to 6Gb/s single-loop reference-less clock and data recovery circuit. The clock frequency multiplier and the reference-less frequency acquisition circuit are used to cover a wide-range data rate. The clock frequency multiplier is proposed to generate the 6GHz clock with low jitter. Also, VCO operates at 1/5-rate frequency of the sampling clock, which has a merit of low power consumption. The proposed circuit achieves 9.56ps RMS jitter, consumes 13.2mW at 6Gb/s and occupies 0.0944mm2 in a 65-nm CMOS technology.

Original languageEnglish
Article number7337379
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
VolumePP
Issue number99
DOIs
Publication statusPublished - 2015

Keywords

  • Clock and data recovery circuit (CDR)
  • Clock frequency multiplier
  • Reference-less
  • Single-loop
  • The reference-less frequency acquisition circuit (RFAC)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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