Abstract
A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator (VCO) and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers (ILFDs) are developed, which are integrated with 12 current mode logic (CML) frequency dividers, a phase frequency detector (PFD), a charge pump (CP), and a loop filter. The fabricated PLL showed a locking range of 282.3-283.7 GHz and a phase noise of -53.5 dBc/Hz at 100 kHz (in-band) and -78.6 dBc/Hz at 10 MHz (out-of-band). Total dc power consumption is 114 mW. The chip occupies <formula><tex>$920 \times 520\ μm^2$</tex></formula> excluding probing pads.
| Original language | English |
|---|---|
| Journal | IEEE Transactions on Terahertz Science and Technology |
| DOIs | |
| Publication status | Accepted/In press - 2018 Jan 1 |
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Keywords
- CMOS integrated circuits
- Fingers
- frequency synthesizer
- Logic gates
- Phase locked loops
- phase-locked loop (PLL)
- Power generation
- ring oscillator
- Transistors
- voltage controlled oscillator (VCO)
- Voltage-controlled oscillators
ASJC Scopus subject areas
- Radiation
- Electrical and Electronic Engineering
Cite this
A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS. / Yoo, Junghwan; Kim, Doyoon; Kim, Jungsoo; Song, Kiryong; Rieh, Jae-Sung.
In: IEEE Transactions on Terahertz Science and Technology, 01.01.2018.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS
AU - Yoo, Junghwan
AU - Kim, Doyoon
AU - Kim, Jungsoo
AU - Song, Kiryong
AU - Rieh, Jae-Sung
PY - 2018/1/1
Y1 - 2018/1/1
N2 - A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator (VCO) and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers (ILFDs) are developed, which are integrated with 12 current mode logic (CML) frequency dividers, a phase frequency detector (PFD), a charge pump (CP), and a loop filter. The fabricated PLL showed a locking range of 282.3-283.7 GHz and a phase noise of -53.5 dBc/Hz at 100 kHz (in-band) and -78.6 dBc/Hz at 10 MHz (out-of-band). Total dc power consumption is 114 mW. The chip occupies $920 \times 520\ μm^2$ excluding probing pads.
AB - A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator (VCO) and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers (ILFDs) are developed, which are integrated with 12 current mode logic (CML) frequency dividers, a phase frequency detector (PFD), a charge pump (CP), and a loop filter. The fabricated PLL showed a locking range of 282.3-283.7 GHz and a phase noise of -53.5 dBc/Hz at 100 kHz (in-band) and -78.6 dBc/Hz at 10 MHz (out-of-band). Total dc power consumption is 114 mW. The chip occupies $920 \times 520\ μm^2$ excluding probing pads.
KW - CMOS integrated circuits
KW - Fingers
KW - frequency synthesizer
KW - Logic gates
KW - Phase locked loops
KW - phase-locked loop (PLL)
KW - Power generation
KW - ring oscillator
KW - Transistors
KW - voltage controlled oscillator (VCO)
KW - Voltage-controlled oscillators
UR - http://www.scopus.com/inward/record.url?scp=85055032227&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85055032227&partnerID=8YFLogxK
U2 - 10.1109/TTHZ.2018.2875796
DO - 10.1109/TTHZ.2018.2875796
M3 - Article
AN - SCOPUS:85055032227
JO - IEEE Transactions on Terahertz Science and Technology
JF - IEEE Transactions on Terahertz Science and Technology
SN - 2156-342X
ER -