TY - JOUR
T1 - A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS
AU - Yoo, Junghwan
AU - Kim, Doyoon
AU - Kim, Jungsoo
AU - Song, Kiryong
AU - Rieh, Jae Sung
N1 - Funding Information:
Manuscript received March 14, 2018; revised October 6, 2018; accepted October 6, 2018. Date of publication October 12, 2018; date of current version December 11, 2018. This work was supported by a grant to the Terahertz Electronic Device Research Laboratory funded by the Defense Acquisition Program Administration and by the Agency for Defense Development (UD180025RD). (Corresponding author: Jae-Sung Rieh.) The authors are with the School of Electrical Engineering, Korea University, Seoul 02841, South Korea (e-mail:,zombiend@korea.ac.kr; kongbob93@ gmail.com; kjs132456@gmail.com; acoor@korea.ac.kr; jsrieh@korea.ac.kr).
Publisher Copyright:
© 2011-2012 IEEE.
PY - 2018/11
Y1 - 2018/11
N2 - A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers are developed, which are integrated with 12 current-mode logic frequency dividers, a phase frequency detector, a charge pump, and a loop filter. The fabricated PLL showed a locking range of 282.3-283.7 GHz and a phase noise of -53.5 dBc/Hz at 100 kHz (in band) and -78.6 dBc/Hz at 10 MHz (out of band). Total dc power consumption is 114 mW. The chip occupies 920 × 520 μm2 excluding probing pads.
AB - A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers are developed, which are integrated with 12 current-mode logic frequency dividers, a phase frequency detector, a charge pump, and a loop filter. The fabricated PLL showed a locking range of 282.3-283.7 GHz and a phase noise of -53.5 dBc/Hz at 100 kHz (in band) and -78.6 dBc/Hz at 10 MHz (out of band). Total dc power consumption is 114 mW. The chip occupies 920 × 520 μm2 excluding probing pads.
KW - CMOS integrated circuits
KW - frequency synthesizer
KW - phase-locked loop (PLL)
KW - ring oscillator
KW - voltage-controlled oscillator (VCO)
UR - http://www.scopus.com/inward/record.url?scp=85055032227&partnerID=8YFLogxK
U2 - 10.1109/TTHZ.2018.2875796
DO - 10.1109/TTHZ.2018.2875796
M3 - Article
AN - SCOPUS:85055032227
VL - 8
SP - 784
EP - 792
JO - IEEE Transactions on Terahertz Science and Technology
JF - IEEE Transactions on Terahertz Science and Technology
SN - 2156-342X
IS - 6
M1 - 8490719
ER -