A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS

Junghwan Yoo, Doyoon Kim, Jungsoo Kim, Kiryong Song, Jae-Sung Rieh

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator (VCO) and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers (ILFDs) are developed, which are integrated with 12 current mode logic (CML) frequency dividers, a phase frequency detector (PFD), a charge pump (CP), and a loop filter. The fabricated PLL showed a locking range of 282.3-283.7 GHz and a phase noise of -53.5 dBc/Hz at 100 kHz (in-band) and -78.6 dBc/Hz at 10 MHz (out-of-band). Total dc power consumption is 114 mW. The chip occupies <formula><tex>$920 \times 520\ &#x03BC;m^2$</tex></formula> excluding probing pads.

Original languageEnglish
JournalIEEE Transactions on Terahertz Science and Technology
DOIs
Publication statusAccepted/In press - 2018 Jan 1

Fingerprint

frequency dividers
Phase locked loops
CMOS
Variable frequency oscillators
Phase noise
voltage controlled oscillators
Electric power utilization
Pumps
Detectors
locking
logic
chips
pumps
injection
filters
rings
detectors

Keywords

  • CMOS integrated circuits
  • Fingers
  • frequency synthesizer
  • Logic gates
  • Phase locked loops
  • phase-locked loop (PLL)
  • Power generation
  • ring oscillator
  • Transistors
  • voltage controlled oscillator (VCO)
  • Voltage-controlled oscillators

ASJC Scopus subject areas

  • Radiation
  • Electrical and Electronic Engineering

Cite this

A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS. / Yoo, Junghwan; Kim, Doyoon; Kim, Jungsoo; Song, Kiryong; Rieh, Jae-Sung.

In: IEEE Transactions on Terahertz Science and Technology, 01.01.2018.

Research output: Contribution to journalArticle

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AU - Rieh, Jae-Sung

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N2 - A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator (VCO) and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers (ILFDs) are developed, which are integrated with 12 current mode logic (CML) frequency dividers, a phase frequency detector (PFD), a charge pump (CP), and a loop filter. The fabricated PLL showed a locking range of 282.3-283.7 GHz and a phase noise of -53.5 dBc/Hz at 100 kHz (in-band) and -78.6 dBc/Hz at 10 MHz (out-of-band). Total dc power consumption is 114 mW. The chip occupies $920 \times 520\ μm^2$ excluding probing pads.

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