A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS

Junghwan Yoo, Doyoon Kim, Jungsoo Kim, Kiryong Song, Jae Sung Rieh

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers are developed, which are integrated with 12 current-mode logic frequency dividers, a phase frequency detector, a charge pump, and a loop filter. The fabricated PLL showed a locking range of 282.3-283.7 GHz and a phase noise of -53.5 dBc/Hz at 100 kHz (in band) and -78.6 dBc/Hz at 10 MHz (out of band). Total dc power consumption is 114 mW. The chip occupies 920 × 520 μm2 excluding probing pads.

Original languageEnglish
Article number8490719
Pages (from-to)784-792
Number of pages9
JournalIEEE Transactions on Terahertz Science and Technology
Volume8
Issue number6
DOIs
Publication statusPublished - 2018 Nov

Keywords

  • CMOS integrated circuits
  • frequency synthesizer
  • phase-locked loop (PLL)
  • ring oscillator
  • voltage-controlled oscillator (VCO)

ASJC Scopus subject areas

  • Radiation
  • Electrical and Electronic Engineering

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