A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS

Junghwan Yoo; Doyoon Kim; Jungsoo Kim; Kiryong Song; Jae-Sung Rieh

doi:10.1109/TTHZ.2018.2875796

A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS

Junghwan Yoo, Doyoon Kim, Jungsoo Kim, Kiryong Song, Jae-Sung Rieh

School of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

3 Citations (Scopus)

Abstract

A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator (VCO) and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers (ILFDs) are developed, which are integrated with 12 current mode logic (CML) frequency dividers, a phase frequency detector (PFD), a charge pump (CP), and a loop filter. The fabricated PLL showed a locking range of 282.3-283.7 GHz and a phase noise of -53.5 dBc/Hz at 100 kHz (in-band) and -78.6 dBc/Hz at 10 MHz (out-of-band). Total dc power consumption is 114 mW. The chip occupies <formula><tex>$920 \times 520\ μm^2$</tex></formula> excluding probing pads.

Original language	English
Journal	IEEE Transactions on Terahertz Science and Technology
DOIs	https://doi.org/10.1109/TTHZ.2018.2875796
Publication status	Accepted/In press - 2018 Jan 1

Keywords

CMOS integrated circuits
Fingers
frequency synthesizer
Logic gates
Phase locked loops
phase-locked loop (PLL)
Power generation
ring oscillator
Transistors
voltage controlled oscillator (VCO)
Voltage-controlled oscillators

ASJC Scopus subject areas

Radiation
Electrical and Electronic Engineering

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title = "A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS",

abstract = "A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator (VCO) and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers (ILFDs) are developed, which are integrated with 12 current mode logic (CML) frequency dividers, a phase frequency detector (PFD), a charge pump (CP), and a loop filter. The fabricated PLL showed a locking range of 282.3-283.7 GHz and a phase noise of -53.5 dBc/Hz at 100 kHz (in-band) and -78.6 dBc/Hz at 10 MHz (out-of-band). Total dc power consumption is 114 mW. The chip occupies $920 \times 520\ μm^2$ excluding probing pads.",

keywords = "CMOS integrated circuits, Fingers, frequency synthesizer, Logic gates, Phase locked loops, phase-locked loop (PLL), Power generation, ring oscillator, Transistors, voltage controlled oscillator (VCO), Voltage-controlled oscillators",

author = "Junghwan Yoo and Doyoon Kim and Jungsoo Kim and Kiryong Song and Jae-Sung Rieh",

year = "2018",

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doi = "10.1109/TTHZ.2018.2875796",

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journal = "IEEE Transactions on Terahertz Science and Technology",

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T1 - A 283-GHz Fully Integrated Phase-Locked Loop Based on 65-nm CMOS

AU - Yoo, Junghwan

AU - Kim, Doyoon

AU - Kim, Jungsoo

AU - Song, Kiryong

AU - Rieh, Jae-Sung

PY - 2018/1/1

Y1 - 2018/1/1

N2 - A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator (VCO) and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers (ILFDs) are developed, which are integrated with 12 current mode logic (CML) frequency dividers, a phase frequency detector (PFD), a charge pump (CP), and a loop filter. The fabricated PLL showed a locking range of 282.3-283.7 GHz and a phase noise of -53.5 dBc/Hz at 100 kHz (in-band) and -78.6 dBc/Hz at 10 MHz (out-of-band). Total dc power consumption is 114 mW. The chip occupies $920 \times 520\ μm^2$ excluding probing pads.

AB - A 283-GHz fully integrated phase-locked loop (PLL) based on a 65-nm CMOS technology is presented. A triple-push ring voltage-controlled oscillator (VCO) and a frequency divider chain (/16,384) composed of 2 injection-locked frequency dividers (ILFDs) are developed, which are integrated with 12 current mode logic (CML) frequency dividers, a phase frequency detector (PFD), a charge pump (CP), and a loop filter. The fabricated PLL showed a locking range of 282.3-283.7 GHz and a phase noise of -53.5 dBc/Hz at 100 kHz (in-band) and -78.6 dBc/Hz at 10 MHz (out-of-band). Total dc power consumption is 114 mW. The chip occupies $920 \times 520\ μm^2$ excluding probing pads.

KW - CMOS integrated circuits

KW - Fingers

KW - frequency synthesizer

KW - Logic gates

KW - Phase locked loops

KW - phase-locked loop (PLL)

KW - Power generation

KW - ring oscillator

KW - Transistors

KW - voltage controlled oscillator (VCO)

KW - Voltage-controlled oscillators

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