Abstract
The process variation among 512 DRAM samples is more than 30% [1]. The performance variation of general circuits is predicted to be over 60% in 2012 [2]. In general, a single-die-based DRAM has a large process variation from chip to chip, which among other parameters, causes tAC (address access time) variation in the application system. In order to reduce the tAC variation, most highspeed SDRAMs adopt a delay-locked loop (DLL) at the cost of additional area and power consumption. For TSV-based stacked dies, large tAC variantion results in higher power consumption due to short circuit current from data conflicts among shared I/Os. Since the number of I/Os for TSV-based stacked DRAM (TSV DRAM) might be 512 or more [3], the additional power consumption can be very high. Even though it is desirable in mobile DRAM to exclude the DLL because of the power cost [3], TSV DRAM for high-speed operation partially adopts a DLL in the master die [4]. Our DLL-based data self-aligner (DBDA) reduces the data conflict time among stacked dies, consuming 283.2μW during read operation at 800Mb/s/pin. It dissipates 4.98μW in self-refresh mode with the help of leakage-current-reduction controller.
| Original language | English |
|---|---|
| Title of host publication | Digest of Technical Papers - IEEE International Solid-State Circuits Conference |
| Pages | 48-49 |
| Number of pages | 2 |
| Volume | 55 |
| DOIs | |
| Publication status | Published - 2012 May 11 |
| Event | 59th International Solid-State Circuits Conference, ISSCC 2012 - San Francisco, CA, United States Duration: 2012 Feb 19 → 2012 Feb 23 |
Other
| Other | 59th International Solid-State Circuits Conference, ISSCC 2012 |
|---|---|
| Country | United States |
| City | San Francisco, CA |
| Period | 12/2/19 → 12/2/23 |
Fingerprint
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
Cite this
A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface. / Lee, Hyun Woo; Lim, Soo Bin; Song, Junyoung; Koo, Ja Beom; Kwon, Dae Han; Kang, Jong Ho; Kim, Yunsaing; Choi, Young Jung; Park, Kunwoo; Chung, Byong Tae; Kim, Chulwoo.
Digest of Technical Papers - IEEE International Solid-State Circuits Conference. Vol. 55 2012. p. 48-49 6176873.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface
AU - Lee, Hyun Woo
AU - Lim, Soo Bin
AU - Song, Junyoung
AU - Koo, Ja Beom
AU - Kwon, Dae Han
AU - Kang, Jong Ho
AU - Kim, Yunsaing
AU - Choi, Young Jung
AU - Park, Kunwoo
AU - Chung, Byong Tae
AU - Kim, Chulwoo
PY - 2012/5/11
Y1 - 2012/5/11
N2 - The process variation among 512 DRAM samples is more than 30% [1]. The performance variation of general circuits is predicted to be over 60% in 2012 [2]. In general, a single-die-based DRAM has a large process variation from chip to chip, which among other parameters, causes tAC (address access time) variation in the application system. In order to reduce the tAC variation, most highspeed SDRAMs adopt a delay-locked loop (DLL) at the cost of additional area and power consumption. For TSV-based stacked dies, large tAC variantion results in higher power consumption due to short circuit current from data conflicts among shared I/Os. Since the number of I/Os for TSV-based stacked DRAM (TSV DRAM) might be 512 or more [3], the additional power consumption can be very high. Even though it is desirable in mobile DRAM to exclude the DLL because of the power cost [3], TSV DRAM for high-speed operation partially adopts a DLL in the master die [4]. Our DLL-based data self-aligner (DBDA) reduces the data conflict time among stacked dies, consuming 283.2μW during read operation at 800Mb/s/pin. It dissipates 4.98μW in self-refresh mode with the help of leakage-current-reduction controller.
AB - The process variation among 512 DRAM samples is more than 30% [1]. The performance variation of general circuits is predicted to be over 60% in 2012 [2]. In general, a single-die-based DRAM has a large process variation from chip to chip, which among other parameters, causes tAC (address access time) variation in the application system. In order to reduce the tAC variation, most highspeed SDRAMs adopt a delay-locked loop (DLL) at the cost of additional area and power consumption. For TSV-based stacked dies, large tAC variantion results in higher power consumption due to short circuit current from data conflicts among shared I/Os. Since the number of I/Os for TSV-based stacked DRAM (TSV DRAM) might be 512 or more [3], the additional power consumption can be very high. Even though it is desirable in mobile DRAM to exclude the DLL because of the power cost [3], TSV DRAM for high-speed operation partially adopts a DLL in the master die [4]. Our DLL-based data self-aligner (DBDA) reduces the data conflict time among stacked dies, consuming 283.2μW during read operation at 800Mb/s/pin. It dissipates 4.98μW in self-refresh mode with the help of leakage-current-reduction controller.
UR - http://www.scopus.com/inward/record.url?scp=84860673091&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84860673091&partnerID=8YFLogxK
U2 - 10.1109/ISSCC.2012.6176873
DO - 10.1109/ISSCC.2012.6176873
M3 - Conference contribution
AN - SCOPUS:84860673091
SN - 9781467303736
VL - 55
SP - 48
EP - 49
BT - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ER -