TY - GEN
T1 - A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface
AU - Lee, Hyun Woo
AU - Lim, Soo Bin
AU - Song, Junyoung
AU - Koo, Ja Beom
AU - Kwon, Dae Han
AU - Kang, Jong Ho
AU - Kim, Yunsaing
AU - Choi, Young Jung
AU - Park, Kunwoo
AU - Chung, Byong Tae
AU - Kim, Chulwoo
PY - 2012
Y1 - 2012
N2 - The process variation among 512 DRAM samples is more than 30% [1]. The performance variation of general circuits is predicted to be over 60% in 2012 [2]. In general, a single-die-based DRAM has a large process variation from chip to chip, which among other parameters, causes tAC (address access time) variation in the application system. In order to reduce the tAC variation, most highspeed SDRAMs adopt a delay-locked loop (DLL) at the cost of additional area and power consumption. For TSV-based stacked dies, large tAC variantion results in higher power consumption due to short circuit current from data conflicts among shared I/Os. Since the number of I/Os for TSV-based stacked DRAM (TSV DRAM) might be 512 or more [3], the additional power consumption can be very high. Even though it is desirable in mobile DRAM to exclude the DLL because of the power cost [3], TSV DRAM for high-speed operation partially adopts a DLL in the master die [4]. Our DLL-based data self-aligner (DBDA) reduces the data conflict time among stacked dies, consuming 283.2μW during read operation at 800Mb/s/pin. It dissipates 4.98μW in self-refresh mode with the help of leakage-current-reduction controller.
AB - The process variation among 512 DRAM samples is more than 30% [1]. The performance variation of general circuits is predicted to be over 60% in 2012 [2]. In general, a single-die-based DRAM has a large process variation from chip to chip, which among other parameters, causes tAC (address access time) variation in the application system. In order to reduce the tAC variation, most highspeed SDRAMs adopt a delay-locked loop (DLL) at the cost of additional area and power consumption. For TSV-based stacked dies, large tAC variantion results in higher power consumption due to short circuit current from data conflicts among shared I/Os. Since the number of I/Os for TSV-based stacked DRAM (TSV DRAM) might be 512 or more [3], the additional power consumption can be very high. Even though it is desirable in mobile DRAM to exclude the DLL because of the power cost [3], TSV DRAM for high-speed operation partially adopts a DLL in the master die [4]. Our DLL-based data self-aligner (DBDA) reduces the data conflict time among stacked dies, consuming 283.2μW during read operation at 800Mb/s/pin. It dissipates 4.98μW in self-refresh mode with the help of leakage-current-reduction controller.
UR - http://www.scopus.com/inward/record.url?scp=84860673091&partnerID=8YFLogxK
U2 - 10.1109/ISSCC.2012.6176873
DO - 10.1109/ISSCC.2012.6176873
M3 - Conference contribution
AN - SCOPUS:84860673091
SN - 9781467303736
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 48
EP - 49
BT - 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012 - Digest of Technical Papers
T2 - 59th International Solid-State Circuits Conference, ISSCC 2012
Y2 - 19 February 2012 through 23 February 2012
ER -