A 2GHz 130mW direct-digital frequency synthesizer with a nonlinear DAC in 55nm CMOS

Taegeun Yoo, Yun Hwan Jung, Hong Chang Yeoh, Yong Sin Kim, Sung Mo Kang, Kwang Hyun Baek

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

Direct-digital frequency synthesizers (DDFSs) have been employed in many frequency-agile communication systems because of their wide bandwidth, fine frequency resolution, and fast frequency-hopping characteristics. Recent developments in DDFSs are towards enhancing performances through reduction of both complexity and power consumption [1-3]. The segmented nonlinear DAC (NLDAC) structures in [1,2] require additional coarse phase information for fine amplitude decoding with a complex decoder. Moreover, the quarter-sine-wave technique incorporated into the segmented NLDACs in [1,2] degrades spectral purity due to the need of the MSB shift DAC that introduces additional offset. Another scheme in [3] reduces complexity and power consumption by replacing the digital-based phase-to-amplitude converter with an analog-based converter, resulting in limited spectral purity. Unlike previous schemes, this work presents comprehensive enhancements in all key areas of a DDFS, the pipelined phase accumulator (PACC), digital decoder, and NLDAC as shown in Fig. 21.3.1. First, the low-power PACC with multi-level momentarily activated bias (M 2AB) is presented to reduce power dissipation. Second, the coarse phase-based consecutive fine-amplitude grouping (C2FAG) scheme reduces the hardware complexity and the power consumption in digital decoder circuits. Third, the mixed-wave conversion topology (MCT) in the NLDAC improves the output spectral purity.

Original languageEnglish
Title of host publication2014 IEEE International Solid-State Circuits Conference, ISSCC 2014 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages364-365
Number of pages2
ISBN (Print)9781479909186
DOIs
Publication statusPublished - 2014
Event2014 61st IEEE International Solid-State Circuits Conference, ISSCC 2014 - San Francisco, CA, United States
Duration: 2014 Feb 92014 Feb 13

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume57
ISSN (Print)0193-6530

Other

Other2014 61st IEEE International Solid-State Circuits Conference, ISSCC 2014
CountryUnited States
CitySan Francisco, CA
Period14/2/914/2/13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Yoo, T., Jung, Y. H., Yeoh, H. C., Kim, Y. S., Kang, S. M., & Baek, K. H. (2014). A 2GHz 130mW direct-digital frequency synthesizer with a nonlinear DAC in 55nm CMOS. In 2014 IEEE International Solid-State Circuits Conference, ISSCC 2014 - Digest of Technical Papers (pp. 364-365). [6757471] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 57). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2014.6757471