## Abstract

A frequency-locked loop (FLL) based spread-spectrum clock generator (SSCG) with a memoryless Newton-Raphson modulation profile is introduced in this paper. The SSCG uses an FLL as a main clock generator. It brings not only an area reduction to the SSCG but also the advantage of having multiple frequency deviations. A double binary-weighted DAC is proposed that modulates the frequency information of the frequency detector using a 1-1-1 MASH $\Delta \Sigma$ modulator. The Newton-Raphson mathematical algorithm is applied to the proposed profile generator in order to generate the optimized nonlinear profile without needing any memory, resulting in a reduction in the area and the power consumption. It also makes it possible to have multiple modulation frequencies. The SSCG can support 14 frequency deviations of $\pm 0.5\%$ to 3.5% in steps of 0.5% and three modulation frequencies of $f _{\rm m}, $2 f _{\rm m} and $3 f _{\rm m}. It achieved an EMI reduction of 19.14 dB with a 0.5% down spreading and a 31 kHz modulation frequency, while employing a core area of 0.076 ${\hbox{mm}} ^{2} in a 0.13-$\mu{\hbox{m}} $ CMOS process and consuming 23.72 mW at 3.5 GHz.

Original language | English |
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Article number | 6155616 |

Pages (from-to) | 1199-1208 |

Number of pages | 10 |

Journal | IEEE Journal of Solid-State Circuits |

Volume | 47 |

Issue number | 5 |

DOIs | |

Publication status | Published - 2012 May |

## Keywords

- Double binary-weighted DAC
- EMI reduction
- Newton-Raphson modulation profile
- frequency modulation
- frequency-locked loop (FLL)
- frequency-to-voltage converter (FVC)
- nonlinear profile
- spread-spectrum clock generator (SSCG)

## ASJC Scopus subject areas

- Electrical and Electronic Engineering