### Abstract

A frequency-locked loop (FLL) based spread-spectrum clock generator (SSCG) with a memoryless Newton-Raphson modulation profile is introduced in this paper. The SSCG uses an FLL as a main clock generator. It brings not only an area reduction to the SSCG but also the advantage of having multiple frequency deviations. A double binary-weighted DAC is proposed that modulates the frequency information of the frequency detector using a 1-1-1 MASH $\Delta \Sigma$ modulator. The Newton-Raphson mathematical algorithm is applied to the proposed profile generator in order to generate the optimized nonlinear profile without needing any memory, resulting in a reduction in the area and the power consumption. It also makes it possible to have multiple modulation frequencies. The SSCG can support 14 frequency deviations of $\pm 0.5\%$ to 3.5% in steps of 0.5% and three modulation frequencies of $f
_{\rm m}, $2 f
_{\rm m} and $3 f
_{\rm m}. It achieved an EMI reduction of 19.14 dB with a 0.5% down spreading and a 31 kHz modulation frequency, while employing a core area of 0.076 ${\hbox{mm}}
^{2} in a 0.13-$\mu{\hbox{m}} $ CMOS process and consuming 23.72 mW at 3.5 GHz.

Original language | English |
---|---|

Article number | 6155616 |

Pages (from-to) | 1199-1208 |

Number of pages | 10 |

Journal | IEEE Journal of Solid-State Circuits |

Volume | 47 |

Issue number | 5 |

DOIs | |

Publication status | Published - 2012 May 1 |

### Fingerprint

### Keywords

- Double binary-weighted DAC
- EMI reduction
- frequency modulation
- frequency-locked loop (FLL)
- frequency-to-voltage converter (FVC)
- Newton-Raphson modulation profile
- nonlinear profile
- spread-spectrum clock generator (SSCG)

### ASJC Scopus subject areas

- Electrical and Electronic Engineering

### Cite this

*IEEE Journal of Solid-State Circuits*,

*47*(5), 1199-1208. [6155616]. https://doi.org/10.1109/JSSC.2012.2183970

**A 3.5 GHz spread-spectrum clock generator with a memoryless newton-raphson modulation profile.** / Hwang, Sewook; Song, Minyoung; Kwak, Young Ho; Jung, Inhwa; Kim, Chulwoo.

Research output: Contribution to journal › Article

*IEEE Journal of Solid-State Circuits*, vol. 47, no. 5, 6155616, pp. 1199-1208. https://doi.org/10.1109/JSSC.2012.2183970

}

TY - JOUR

T1 - A 3.5 GHz spread-spectrum clock generator with a memoryless newton-raphson modulation profile

AU - Hwang, Sewook

AU - Song, Minyoung

AU - Kwak, Young Ho

AU - Jung, Inhwa

AU - Kim, Chulwoo

PY - 2012/5/1

Y1 - 2012/5/1

N2 - A frequency-locked loop (FLL) based spread-spectrum clock generator (SSCG) with a memoryless Newton-Raphson modulation profile is introduced in this paper. The SSCG uses an FLL as a main clock generator. It brings not only an area reduction to the SSCG but also the advantage of having multiple frequency deviations. A double binary-weighted DAC is proposed that modulates the frequency information of the frequency detector using a 1-1-1 MASH $\Delta \Sigma$ modulator. The Newton-Raphson mathematical algorithm is applied to the proposed profile generator in order to generate the optimized nonlinear profile without needing any memory, resulting in a reduction in the area and the power consumption. It also makes it possible to have multiple modulation frequencies. The SSCG can support 14 frequency deviations of $\pm 0.5\%$ to 3.5% in steps of 0.5% and three modulation frequencies of $f \rm m, $2 f \rm m and $3 f \rm m. It achieved an EMI reduction of 19.14 dB with a 0.5% down spreading and a 31 kHz modulation frequency, while employing a core area of 0.076 ${\hbox{mm}} 2 in a 0.13-$\mu{\hbox{m}} $ CMOS process and consuming 23.72 mW at 3.5 GHz.

AB - A frequency-locked loop (FLL) based spread-spectrum clock generator (SSCG) with a memoryless Newton-Raphson modulation profile is introduced in this paper. The SSCG uses an FLL as a main clock generator. It brings not only an area reduction to the SSCG but also the advantage of having multiple frequency deviations. A double binary-weighted DAC is proposed that modulates the frequency information of the frequency detector using a 1-1-1 MASH $\Delta \Sigma$ modulator. The Newton-Raphson mathematical algorithm is applied to the proposed profile generator in order to generate the optimized nonlinear profile without needing any memory, resulting in a reduction in the area and the power consumption. It also makes it possible to have multiple modulation frequencies. The SSCG can support 14 frequency deviations of $\pm 0.5\%$ to 3.5% in steps of 0.5% and three modulation frequencies of $f \rm m, $2 f \rm m and $3 f \rm m. It achieved an EMI reduction of 19.14 dB with a 0.5% down spreading and a 31 kHz modulation frequency, while employing a core area of 0.076 ${\hbox{mm}} 2 in a 0.13-$\mu{\hbox{m}} $ CMOS process and consuming 23.72 mW at 3.5 GHz.

KW - Double binary-weighted DAC

KW - EMI reduction

KW - frequency modulation

KW - frequency-locked loop (FLL)

KW - frequency-to-voltage converter (FVC)

KW - Newton-Raphson modulation profile

KW - nonlinear profile

KW - spread-spectrum clock generator (SSCG)

UR - http://www.scopus.com/inward/record.url?scp=84862820804&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84862820804&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2012.2183970

DO - 10.1109/JSSC.2012.2183970

M3 - Article

AN - SCOPUS:84862820804

VL - 47

SP - 1199

EP - 1208

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 5

M1 - 6155616

ER -