Abstract
A 4 x 5-Gb/s reference-less receiver is proposed in a 0.13-μm CMOS technology. In the proposed reference-less clock and data recovery (CDR) circuit, asynchronous sampling-based frequency acquisition is proposed to achieve a fast frequency locking, and VCO calibration is proposed to attain a constant loop bandwidth. To reduce noise caused by multiple VCOs, a clock signal is forwarded from the main channel to the subchannels, and skews between the channels are compensated by a skew compensation algorithm. In the main channel, the reference-less CDR achieves a 1.12-μs locking time, and the measured standard deviation of VCO gain is reduced from 0.33 to 0.08. The recovered clock jitter in the main channel is 1.591 psrms, and the power consumption of the main channel and the subchannels are 3.53 and 2.16 mW/Gb/s, respectively.
| Original language | English |
|---|---|
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| DOIs | |
| Publication status | Accepted/In press - 2016 Feb 11 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Hardware and Architecture
- Software
Cite this
A 4 x 5-Gb/s 1.12-μs Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels. / Song, Junyoung; Hwang, Sewook; Kim, Chulwoo.
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11.02.2016.Research output: Contribution to journal › Article
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TY - JOUR
T1 - A 4 x 5-Gb/s 1.12-μs Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels
AU - Song, Junyoung
AU - Hwang, Sewook
AU - Kim, Chulwoo
PY - 2016/2/11
Y1 - 2016/2/11
N2 - A 4 x 5-Gb/s reference-less receiver is proposed in a 0.13-μm CMOS technology. In the proposed reference-less clock and data recovery (CDR) circuit, asynchronous sampling-based frequency acquisition is proposed to achieve a fast frequency locking, and VCO calibration is proposed to attain a constant loop bandwidth. To reduce noise caused by multiple VCOs, a clock signal is forwarded from the main channel to the subchannels, and skews between the channels are compensated by a skew compensation algorithm. In the main channel, the reference-less CDR achieves a 1.12-μs locking time, and the measured standard deviation of VCO gain is reduced from 0.33 to 0.08. The recovered clock jitter in the main channel is 1.591 psrms, and the power consumption of the main channel and the subchannels are 3.53 and 2.16 mW/Gb/s, respectively.
AB - A 4 x 5-Gb/s reference-less receiver is proposed in a 0.13-μm CMOS technology. In the proposed reference-less clock and data recovery (CDR) circuit, asynchronous sampling-based frequency acquisition is proposed to achieve a fast frequency locking, and VCO calibration is proposed to attain a constant loop bandwidth. To reduce noise caused by multiple VCOs, a clock signal is forwarded from the main channel to the subchannels, and skews between the channels are compensated by a skew compensation algorithm. In the main channel, the reference-less CDR achieves a 1.12-μs locking time, and the measured standard deviation of VCO gain is reduced from 0.33 to 0.08. The recovered clock jitter in the main channel is 1.591 psrms, and the power consumption of the main channel and the subchannels are 3.53 and 2.16 mW/Gb/s, respectively.
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U2 - 10.1109/TVLSI.2016.2520584
DO - 10.1109/TVLSI.2016.2520584
M3 - Article
AN - SCOPUS:84958673747
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
ER -