A 400 MHz-1.5 GHz all digital integer-N PLL with a reference spur reduction technique

Junyoung Song, Sewook Hwang, Tae Chan Kim, Chulwoo Kim

Research output: Contribution to journalArticle

Abstract

In this Letter, 400 MHz-1.5 GHz all digital integer-N PLL with a reference spur reduction is proposed. A reference spur is occurred by updating DCO control code at every reference clock period. To reduce a reference spur component, the phase detector which transfers phase error information only when phase error is detected has been designed. The measured clock jitter is 2.528 psrms at 1.5 GHz operation, and 3.991 psrms at 400 MHz operation. The ADPLL occupies 0.088 mm2, and consumes 1.19 mW at 1.5 GHz. This ADPLL is implemented in 65 nm CMOS technology.

Original languageEnglish
Pages (from-to)183-189
Number of pages7
JournalAnalog Integrated Circuits and Signal Processing
Volume79
Issue number1
DOIs
Publication statusPublished - 2014 Jan 1

Keywords

  • All-digital PLL
  • Integer-N PLL
  • Spur reduction
  • Wide-range PLL

ASJC Scopus subject areas

  • Surfaces, Coatings and Films
  • Hardware and Architecture
  • Signal Processing

Fingerprint Dive into the research topics of 'A 400 MHz-1.5 GHz all digital integer-N PLL with a reference spur reduction technique'. Together they form a unique fingerprint.

  • Cite this